{"id":2225828,"url":"http://patchwork.ozlabs.org/api/patches/2225828/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421162912.3295598-4-jim.shu@sifive.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421162912.3295598-4-jim.shu@sifive.com>","list_archive_url":null,"date":"2026-04-21T16:29:10","name":"[v2,3/5] accel/tcg: Provide early AS translate function","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2123eacf94c179185d82cd1160cb2b64d737cee4","submitter":{"id":83153,"url":"http://patchwork.ozlabs.org/api/people/83153/?format=json","name":"Jim Shu","email":"jim.shu@sifive.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421162912.3295598-4-jim.shu@sifive.com/mbox/","series":[{"id":500851,"url":"http://patchwork.ozlabs.org/api/series/500851/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500851","date":"2026-04-21T16:29:09","name":"Defer the IOMMU translation and support access_type","version":2,"mbox":"http://patchwork.ozlabs.org/series/500851/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225828/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225828/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=PkFTKG8x;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0SYW5ZhTz1yGt\n\tfor ; Wed, 22 Apr 2026 02:31:59 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFDzE-0000Mq-6i; Tue, 21 Apr 2026 12:30:08 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wFDz4-00005P-3i\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 12:30:01 -0400","from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wFDyw-0005jR-50\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 12:29:55 -0400","by mail-pj1-x1030.google.com with SMTP id\n 98e67ed59e1d1-35da2d35eccso3204140a91.0\n for ; Tue, 21 Apr 2026 09:29:43 -0700 (PDT)","from hsinchu26.internal.sifive.com ([210.176.154.34])\n by smtp.gmail.com with ESMTPSA id\n 98e67ed59e1d1-36140ff2e1esm13529470a91.8.2026.04.21.09.29.36\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 21 Apr 2026 09:29:41 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=sifive.com; s=google; t=1776788982; x=1777393782; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=++ZGjXwMqfSingAg7xdviV4c5zJjqE5XGviD8tj3+/Q=;\n b=PkFTKG8xDuDmPDC9/CB01/h7Deu793FTb+rcmCbAj1r87Q6LjnTWjUAcOx45KA/d6P\n /JFxdmgec9TLPchquSLFD6jSfAg09rvpOxPUGjQgvxLQKSO8JbmNwltrr9GVfGBdyaAX\n 4Jvi6o/8oeapX8PGVeVoHRExSG6c+CzNqOdWgMRgX7jdAj+bH3FYWrE8fy5Vmaz5jgCR\n 9HMOiEBVhsnyWbB7A0kT2xlcgxkjmqQ1j7jXLA2eZmLJq4U5dPTRVeUCb8EVhI3UHP1f\n WP5k3yoWnM7WlPc/PCHQLaWdSl0Z1YKak23mPSPkK2KWo166oQBHl8uudSibBsW/DBQd\n mUNA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1776788982; x=1777393782;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=++ZGjXwMqfSingAg7xdviV4c5zJjqE5XGviD8tj3+/Q=;\n b=lhKJsfO4YhT4b2QXflGfAkOkxjgU5pBMY6o6uYCk/7ylMz0VT2nqacCdvywjNNXkxZ\n h7slJOh+obPs9IJNl8VcaXVT1R2WwcnGwJrU+BEddr6UUqIHwY9eFm1He7mA8eKuoiK9\n rx2epKUosiZFBCojQiXeQoyYGeqBykd2p/WgGV2dX/DmIHFzMjiwCAuWs0G1lOZgkPZQ\n DCero46IgEtbfJgCWNr/V2ylqCx3eZrvpbAswK7+ciPMVn8/e2vjNti/IqvamEyCbY6E\n ULT725539WIGEYwsszoiqwL6lp89KuWqipiEVeexLf7II0ngtyjebClG/rbZM+oCAZSP\n eGJw==","X-Gm-Message-State":"AOJu0YwJyV3rctfX3k4PMnKiGqSYA1aS5lwzUoemqah52SZflgQVNt4a\n IWAgTTh5emW6oo8nbrTNoLyY/EPXlC9ysRZ5hg5MS14J3cywqdfi0Xv/b7cGnCbPrsrQuU51WUn\n 5Tmx4nJ5UkAOK1L3sXPT6Ob8zDp2y5pGyL4/fypS+tYz/zfWiL2Wq+sda2aYCnFpZpQC341wwOq\n KtRJafaOrSbYr0zQpXBLP/achDmPiMcz+CxUoLgFF8","X-Gm-Gg":"AeBDieuaTNQ55stklJvaHRMdfM538xjJZnscTVhvjP1cMzva9IV4zKZgOuhjIADrmHA\n 0zmU4q6QqM4COh4QuR9f9zxYuRBbWfcbImGXeRCp/xT4ZV+qt1uODIsvRydFlWIw93+HB/rt2R/\n vymeNCGyTG8lPSpvJB4xc1ySOv8Jrr0BJVAc5d8KnwBRGWNHyFMZhSqXn0/Rizj3glZ1W37NcwV\n LF1d0LvBdtsO+TrSgxxY2SINaC4XwFtZeLnS41g3jHpJQ4UUa8ETrClqTJ/2lNlR2/hql1NGPAy\n JPWPpTyPAIjK6lqzoHG3nJAX+J5MtxK9qJ4fXNN+7sKOnNqhSYs1Tmdhin6LgffsHCBcRMqrsYQ\n aq5Z3Ofv0loGxNZQnmtdYii5Kt2/JgCIyxR+bzFZzM0Nzb94oKs2mCSzLDuoLB1Mst54oQCN3o9\n gSD3r7c2NbPky6Cl/E8ujnD2TPev9NtFv6IKXy9SRSh4Wrqm7vMTPpToQ=","X-Received":"by 2002:a17:90b:3f8f:b0:35c:30a8:341 with SMTP id\n 98e67ed59e1d1-3614046cd3amr19271795a91.13.1776788982053;\n Tue, 21 Apr 2026 09:29:42 -0700 (PDT)","From":"Jim Shu ","To":"qemu-devel@nongnu.org,\n\tqemu-riscv@nongnu.org","Cc":"Richard Henderson ,\n Paolo Bonzini ,\n =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ,\n Marcel Apfelbaum ,\n Yanan Wang , Zhao Liu ,\n Peter Xu , Michael Rolnik ,\n Helge Deller , Song Gao ,\n Laurent Vivier ,\n \"Edgar E. Iglesias\" ,\n Aurelien Jarno , Jiaxun Yang ,\n Aleksandar Rikalo , Stafford Horne ,\n Nicholas Piggin , Chinmay Rath ,\n Glenn Miles , Palmer Dabbelt ,\n Alistair Francis , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu ,\n Yoshinori Sato ,\n Ilya Leoshkevich , David Hildenbrand ,\n Cornelia Huck , Eric Farman ,\n Matthew Rosato ,\n Mark Cave-Ayland ,\n Artyom Tarasenko ,\n Bastian Koppelmann ,\n Max Filippov ,\n qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs),\n qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu ","Subject":"[PATCH v2 3/5] accel/tcg: Provide early AS translate function","Date":"Wed, 22 Apr 2026 00:29:10 +0800","Message-ID":"<20260421162912.3295598-4-jim.shu@sifive.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260421162912.3295598-1-jim.shu@sifive.com>","References":"<20260421162912.3295598-1-jim.shu@sifive.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::1030;\n envelope-from=jim.shu@sifive.com; helo=mail-pj1-x1030.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"New early AS translate function will skip IOMMU translation. It will\nreturn IOMMU region if finding it. Original function is renamed to the\nlate translate function.\n\nIt is preparation commit of IOMMU lazy translation.\n\nSigned-off-by: Jim Shu \n---\n accel/tcg/cputlb.c | 6 ++---\n include/accel/tcg/iommu.h | 13 +++++++----\n system/physmem.c | 46 ++++++++++++++++++++++++++++++++++++---\n 3 files changed, 55 insertions(+), 10 deletions(-)","diff":"diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c\nindex 4ca4152579b..f0c049e1551 100644\n--- a/accel/tcg/cputlb.c\n+++ b/accel/tcg/cputlb.c\n@@ -1049,9 +1049,9 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx,\n \n prot = full->prot;\n asidx = cpu_asidx_from_attrs(cpu, full->attrs);\n- section = address_space_translate_for_iotlb(cpu, asidx, paddr_page,\n- &xlat, &sz, full->attrs, &prot,\n- access_type);\n+ section = address_space_translate_for_iotlb_late(cpu, asidx, paddr_page,\n+ &xlat, &sz, full->attrs,\n+ &prot);\n assert(sz >= TARGET_PAGE_SIZE);\n \n tlb_debug(\"vaddr=%016\" VADDR_PRIx \" paddr=0x\" HWADDR_FMT_plx\ndiff --git a/include/accel/tcg/iommu.h b/include/accel/tcg/iommu.h\nindex 30655aab4ba..11e3d63d798 100644\n--- a/include/accel/tcg/iommu.h\n+++ b/include/accel/tcg/iommu.h\n@@ -15,10 +15,15 @@\n #include \"exec/memattrs.h\"\n \n MemoryRegionSection *\n-address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,\n- hwaddr *xlat, hwaddr *plen,\n- MemTxAttrs attrs, int *prot,\n- MMUAccessType access_type);\n+address_space_translate_for_iotlb_early(CPUState *cpu, int asidx, hwaddr addr,\n+ hwaddr *xlat, hwaddr *plen,\n+ MemTxAttrs attrs, int *prot);\n+\n+MemoryRegionSection *\n+address_space_translate_for_iotlb_late(CPUState *cpu, int asidx, hwaddr addr,\n+ hwaddr *xlat, hwaddr *plen,\n+ MemTxAttrs attrs, int *prot,\n+ MMUAccessType access_type);\n \n #endif\n \ndiff --git a/system/physmem.c b/system/physmem.c\nindex d3d111392c1..72c564b94a5 100644\n--- a/system/physmem.c\n+++ b/system/physmem.c\n@@ -682,11 +682,11 @@ void tcg_iommu_init_notifier_list(CPUState *cpu)\n }\n \n /* Called from RCU critical section */\n-MemoryRegionSection *\n+static MemoryRegionSection *\n address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_addr,\n hwaddr *xlat, hwaddr *plen,\n MemTxAttrs attrs, int *prot,\n- MMUAccessType access_type)\n+ MMUAccessType access_type, bool early_trans)\n {\n MemoryRegionSection *section;\n IOMMUMemoryRegion *iommu_mr;\n@@ -710,6 +710,11 @@ address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_addr,\n iommu_idx = imrc->attrs_to_index(iommu_mr, attrs);\n tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx);\n \n+ /* Defer the iommu translation */\n+ if (early_trans) {\n+ break;\n+ }\n+\n if (access_type == MMU_DATA_STORE) {\n iommu_flags = IOMMU_WO;\n } else {\n@@ -737,7 +742,8 @@ address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_addr,\n d = flatview_to_dispatch(address_space_to_flatview(iotlb.target_as));\n }\n \n- assert(!memory_region_is_iommu(section->mr));\n+ /* For late translation, IOMMU region translation should be finished */\n+ assert(early_trans || !memory_region_is_iommu(section->mr));\n *xlat = addr;\n return section;\n \n@@ -755,6 +761,40 @@ translate_fail:\n return &d->map.sections[PHYS_SECTION_UNASSIGNED];\n }\n \n+/*\n+ * address_space_translate_for_iotlb_early: translate address without\n+ * performing IOMMU translation. This is used for CPU TLB setup.\n+ *\n+ * Called from RCU critical section.\n+ */\n+MemoryRegionSection *\n+address_space_translate_for_iotlb_early(CPUState *cpu, int asidx,\n+ hwaddr orig_addr,\n+ hwaddr *xlat, hwaddr *plen,\n+ MemTxAttrs attrs, int *prot)\n+{\n+ /* access_type doesn't matter for early translation */\n+ return address_space_translate_for_iotlb(cpu, asidx, orig_addr, xlat, plen,\n+ attrs, prot, MMU_DATA_LOAD, true);\n+}\n+\n+/*\n+ * address_space_translate_for_iotlb_late: translate address with\n+ * performing IOMMU translation. This is used for lazy IOMMU translation.\n+ *\n+ * Called from RCU critical section.\n+ */\n+MemoryRegionSection *\n+address_space_translate_for_iotlb_late(CPUState *cpu, int asidx,\n+ hwaddr orig_addr,\n+ hwaddr *xlat, hwaddr *plen,\n+ MemTxAttrs attrs, int *prot,\n+ MMUAccessType access_type)\n+{\n+ return address_space_translate_for_iotlb(cpu, asidx, orig_addr, xlat, plen,\n+ attrs, prot, access_type, false);\n+}\n+\n #endif /* CONFIG_TCG */\n \n void cpu_address_space_init(CPUState *cpu, int asidx,\n","prefixes":["v2","3/5"]}