{"id":2225827,"url":"http://patchwork.ozlabs.org/api/patches/2225827/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421162912.3295598-2-jim.shu@sifive.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421162912.3295598-2-jim.shu@sifive.com>","list_archive_url":null,"date":"2026-04-21T16:29:08","name":"[v2,1/5] accel/tcg: Pass access_type as an argument of tlb_set_page*()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"99ee4a3ea63c11e7f327ba5e8f0570cfd561cbfb","submitter":{"id":83153,"url":"http://patchwork.ozlabs.org/api/people/83153/?format=json","name":"Jim Shu","email":"jim.shu@sifive.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421162912.3295598-2-jim.shu@sifive.com/mbox/","series":[{"id":500851,"url":"http://patchwork.ozlabs.org/api/series/500851/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500851","date":"2026-04-21T16:29:09","name":"Defer the IOMMU translation and support access_type","version":2,"mbox":"http://patchwork.ozlabs.org/series/500851/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225827/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225827/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=idLIqPgu;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Iglesias\" ,\n Aurelien Jarno , Jiaxun Yang ,\n Aleksandar Rikalo , Stafford Horne ,\n Nicholas Piggin , Chinmay Rath ,\n Glenn Miles , Palmer Dabbelt ,\n Alistair Francis , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu ,\n Yoshinori Sato ,\n Ilya Leoshkevich , David Hildenbrand ,\n Cornelia Huck , Eric Farman ,\n Matthew Rosato ,\n Mark Cave-Ayland ,\n Artyom Tarasenko ,\n Bastian Koppelmann ,\n Max Filippov ,\n qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs),\n qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu ","Subject":"[PATCH v2 1/5] accel/tcg: Pass access_type as an argument of\n tlb_set_page*()","Date":"Wed, 22 Apr 2026 00:29:08 +0800","Message-ID":"<20260421162912.3295598-2-jim.shu@sifive.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260421162912.3295598-1-jim.shu@sifive.com>","References":"<20260421162912.3295598-1-jim.shu@sifive.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::102b;\n envelope-from=jim.shu@sifive.com; helo=mail-pj1-x102b.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Pass the access_type so that we could know CPU will do the read or\nwrite access. Then, CPU can fill the CPUTLBEntry[Full] of the specific\npermission (@prot).\n\nIt is fine for address_space_translate*() to return different section of\nread and write access. tlb_set_page*() only sets 'CPUTLBEntry.addr_*'\nfor specific @prot, so access from another @prot will only get TLB miss\nand start to overwrite 'CPUTLBEntry[Full]' with new @prot.\n\nIt is the preliminary patch of next commit to pass the iommu_flags\nto IOMMUMemoryRegion from access_type.\n\nSigned-off-by: Jim Shu \n\n---\n accel/tcg/cputlb.c | 14 ++++++++------\n include/exec/cputlb.h | 11 +++++++----\n target/alpha/helper.c | 2 +-\n target/avr/helper.c | 3 ++-\n target/hppa/mem_helper.c | 1 -\n target/i386/tcg/system/excp_helper.c | 3 ++-\n target/loongarch/tcg/tlb_helper.c | 2 +-\n target/m68k/helper.c | 10 +++++++---\n target/microblaze/helper.c | 8 ++++----\n target/mips/tcg/system/tlb_helper.c | 4 ++--\n target/or1k/mmu.c | 2 +-\n target/ppc/mmu_helper.c | 2 +-\n target/riscv/cpu_helper.c | 2 +-\n target/rx/cpu.c | 3 ++-\n target/s390x/tcg/excp_helper.c | 2 +-\n target/sh4/helper.c | 3 ++-\n target/sparc/mmu_helper.c | 6 +++---\n target/tricore/helper.c | 2 +-\n target/xtensa/helper.c | 3 ++-\n 19 files changed, 48 insertions(+), 35 deletions(-)","diff":"diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c\nindex d6115bbb0a4..3bc951603dc 100644\n--- a/accel/tcg/cputlb.c\n+++ b/accel/tcg/cputlb.c\n@@ -1022,7 +1022,8 @@ static inline void tlb_set_compare(CPUTLBEntryFull *full, CPUTLBEntry *ent,\n * critical section.\n */\n void tlb_set_page_full(CPUState *cpu, int mmu_idx,\n- vaddr addr, CPUTLBEntryFull *full)\n+ vaddr addr, MMUAccessType access_type,\n+ CPUTLBEntryFull *full)\n {\n CPUTLB *tlb = &cpu->neg.tlb;\n CPUTLBDesc *desc = &tlb->d[mmu_idx];\n@@ -1185,7 +1186,8 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx,\n \n void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,\n hwaddr paddr, MemTxAttrs attrs, int prot,\n- int mmu_idx, vaddr size)\n+ MMUAccessType access_type, int mmu_idx,\n+ vaddr size)\n {\n CPUTLBEntryFull full = {\n .phys_addr = paddr,\n@@ -1195,15 +1197,15 @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,\n };\n \n assert(is_power_of_2(size));\n- tlb_set_page_full(cpu, mmu_idx, addr, &full);\n+ tlb_set_page_full(cpu, mmu_idx, addr, access_type, &full);\n }\n \n void tlb_set_page(CPUState *cpu, vaddr addr,\n- hwaddr paddr, int prot,\n+ hwaddr paddr, int prot, MMUAccessType access_type,\n int mmu_idx, vaddr size)\n {\n tlb_set_page_with_attrs(cpu, addr, paddr, MEMTXATTRS_UNSPECIFIED,\n- prot, mmu_idx, size);\n+ prot, access_type, mmu_idx, size);\n }\n \n /**\n@@ -1245,7 +1247,7 @@ static bool tlb_fill_align(CPUState *cpu, vaddr addr, MMUAccessType type,\n if (ops->tlb_fill_align) {\n if (ops->tlb_fill_align(cpu, &full, addr, type, mmu_idx,\n memop, size, probe, ra)) {\n- tlb_set_page_full(cpu, mmu_idx, addr, &full);\n+ tlb_set_page_full(cpu, mmu_idx, addr, type, &full);\n return true;\n }\n } else {\ndiff --git a/include/exec/cputlb.h b/include/exec/cputlb.h\nindex 3a9603a6965..47fa4302a9a 100644\n--- a/include/exec/cputlb.h\n+++ b/include/exec/cputlb.h\n@@ -41,6 +41,7 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);\n * @cpu: CPU context\n * @mmu_idx: mmu index of the tlb to modify\n * @addr: virtual address of the entry to add\n+ * @access_type: access was read/write/execute\n * @full: the details of the tlb entry\n *\n * Add an entry to @cpu tlb index @mmu_idx. All of the fields of\n@@ -56,6 +57,7 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length);\n * used by tlb_flush_page.\n */\n void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,\n+ MMUAccessType access_type,\n CPUTLBEntryFull *full);\n \n /**\n@@ -65,6 +67,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,\n * @paddr: physical address of the page\n * @attrs: memory transaction attributes\n * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)\n+ * @access_type: access was read/write/execute\n * @mmu_idx: MMU index to insert TLB entry for\n * @size: size of the page in bytes\n *\n@@ -81,9 +84,9 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,\n * used by tlb_flush_page.\n */\n void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,\n- hwaddr paddr, MemTxAttrs attrs,\n- int prot, int mmu_idx, vaddr size);\n-\n+ hwaddr paddr, MemTxAttrs attrs, int prot,\n+ MMUAccessType access_type, int mmu_idx,\n+ vaddr size);\n /**\n * tlb_set_page:\n *\n@@ -92,7 +95,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,\n * as a convenience for CPUs which don't use memory transaction attributes.\n */\n void tlb_set_page(CPUState *cpu, vaddr addr,\n- hwaddr paddr, int prot,\n+ hwaddr paddr, int prot, MMUAccessType access_type,\n int mmu_idx, vaddr size);\n \n #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)\ndiff --git a/target/alpha/helper.c b/target/alpha/helper.c\nindex 179dc2dc7ae..7645ff27e20 100644\n--- a/target/alpha/helper.c\n+++ b/target/alpha/helper.c\n@@ -328,7 +328,7 @@ bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,\n }\n \n tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,\n- prot, mmu_idx, TARGET_PAGE_SIZE);\n+ prot, access_type, mmu_idx, TARGET_PAGE_SIZE);\n return true;\n }\n \ndiff --git a/target/avr/helper.c b/target/avr/helper.c\nindex 365c8c60e19..4f536f08676 100644\n--- a/target/avr/helper.c\n+++ b/target/avr/helper.c\n@@ -143,7 +143,8 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n prot = PAGE_READ | PAGE_WRITE;\n }\n \n- tlb_set_page(cs, address, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);\n+ tlb_set_page(cs, address, paddr, prot, access_type, mmu_idx,\n+ TARGET_PAGE_SIZE);\n return true;\n }\n \ndiff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c\nindex ffbad8acfd2..63606c19d07 100644\n--- a/target/hppa/mem_helper.c\n+++ b/target/hppa/mem_helper.c\n@@ -482,7 +482,6 @@ bool hppa_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr,\n out->prot = prot;\n out->attrs = MEMTXATTRS_UNSPECIFIED;\n out->lg_page_size = TARGET_PAGE_BITS;\n-\n return true;\n }\n \ndiff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/excp_helper.c\nindex d7ea77c8558..0fdae83f0a2 100644\n--- a/target/i386/tcg/system/excp_helper.c\n+++ b/target/i386/tcg/system/excp_helper.c\n@@ -628,7 +628,8 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,\n tlb_set_page_with_attrs(cs, addr & TARGET_PAGE_MASK,\n out.paddr & TARGET_PAGE_MASK,\n cpu_get_mem_attrs(env),\n- out.prot, mmu_idx, out.page_size);\n+ out.prot, access_type, mmu_idx,\n+ out.page_size);\n return true;\n }\n \ndiff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c\nindex c0fd8527fe9..f84a62e2861 100644\n--- a/target/loongarch/tcg/tlb_helper.c\n+++ b/target/loongarch/tcg/tlb_helper.c\n@@ -669,7 +669,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n prot = context.prot;\n tlb_set_page(cs, address & TARGET_PAGE_MASK,\n physical & TARGET_PAGE_MASK, prot,\n- mmu_idx, TARGET_PAGE_SIZE);\n+ access_type, mmu_idx, TARGET_PAGE_SIZE);\n qemu_log_mask(CPU_LOG_MMU,\n \"%s address=%\" VADDR_PRIx \" physical \" HWADDR_FMT_plx\n \" prot %d\\n\", __func__, address, physical, prot);\ndiff --git a/target/m68k/helper.c b/target/m68k/helper.c\nindex 9bab1843892..0de0a7dd248 100644\n--- a/target/m68k/helper.c\n+++ b/target/m68k/helper.c\n@@ -969,7 +969,7 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n tlb_set_page(cs, address & TARGET_PAGE_MASK,\n address & TARGET_PAGE_MASK,\n PAGE_READ | PAGE_WRITE | PAGE_EXEC,\n- mmu_idx, TARGET_PAGE_SIZE);\n+ qemu_access_type, mmu_idx, TARGET_PAGE_SIZE);\n return true;\n }\n \n@@ -989,7 +989,8 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n address, access_type, &page_size);\n if (likely(ret == 0)) {\n tlb_set_page(cs, address & TARGET_PAGE_MASK,\n- physical & TARGET_PAGE_MASK, prot, mmu_idx, page_size);\n+ physical & TARGET_PAGE_MASK, prot, qemu_access_type,\n+ mmu_idx, page_size);\n return true;\n }\n \n@@ -1461,6 +1462,7 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read)\n int prot;\n int ret;\n target_ulong page_size;\n+ MMUAccessType qemu_access_type;\n \n access_type = ACCESS_PTEST;\n if (env->dfc & 4) {\n@@ -1468,9 +1470,11 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read)\n }\n if ((env->dfc & 3) == 2) {\n access_type |= ACCESS_CODE;\n+ qemu_access_type = MMU_INST_FETCH;\n }\n if (!is_read) {\n access_type |= ACCESS_STORE;\n+ qemu_access_type = MMU_DATA_STORE;\n }\n \n env->mmu.mmusr = 0;\n@@ -1480,7 +1484,7 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read)\n if (ret == 0) {\n tlb_set_page(env_cpu(env), addr & TARGET_PAGE_MASK,\n physical & TARGET_PAGE_MASK,\n- prot, access_type & ACCESS_SUPER ?\n+ prot, qemu_access_type, access_type & ACCESS_SUPER ?\n MMU_KERNEL_IDX : MMU_USER_IDX, page_size);\n }\n }\ndiff --git a/target/microblaze/helper.c b/target/microblaze/helper.c\nindex a1857b72172..2bdf8c3ea03 100644\n--- a/target/microblaze/helper.c\n+++ b/target/microblaze/helper.c\n@@ -101,8 +101,8 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n /* MMU disabled or not available. */\n address &= TARGET_PAGE_MASK;\n prot = PAGE_RWX;\n- tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx,\n- TARGET_PAGE_SIZE);\n+ tlb_set_page_with_attrs(cs, address, address, attrs, prot, access_type,\n+ mmu_idx, TARGET_PAGE_SIZE);\n return true;\n }\n \n@@ -113,8 +113,8 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n \n qemu_log_mask(CPU_LOG_MMU, \"MMU map mmu=%d v=%x p=%x prot=%x\\n\",\n mmu_idx, vaddr, paddr, lu.prot);\n- tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, mmu_idx,\n- TARGET_PAGE_SIZE);\n+ tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, access_type,\n+ mmu_idx, TARGET_PAGE_SIZE);\n return true;\n }\n \ndiff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/tlb_helper.c\nindex 566924b079e..bf08ba29d02 100644\n--- a/target/mips/tcg/system/tlb_helper.c\n+++ b/target/mips/tcg/system/tlb_helper.c\n@@ -934,7 +934,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n if (ret == TLBRET_MATCH) {\n tlb_set_page(cs, address & TARGET_PAGE_MASK,\n physical & TARGET_PAGE_MASK, prot,\n- mmu_idx, TARGET_PAGE_SIZE);\n+ access_type, mmu_idx, TARGET_PAGE_SIZE);\n return true;\n }\n #if !defined(TARGET_MIPS64)\n@@ -952,7 +952,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n if (ret == TLBRET_MATCH) {\n tlb_set_page(cs, address & TARGET_PAGE_MASK,\n physical & TARGET_PAGE_MASK, prot,\n- mmu_idx, TARGET_PAGE_SIZE);\n+ access_type, mmu_idx, TARGET_PAGE_SIZE);\n return true;\n }\n }\ndiff --git a/target/or1k/mmu.c b/target/or1k/mmu.c\nindex 315debaf3e5..c14f03081e1 100644\n--- a/target/or1k/mmu.c\n+++ b/target/or1k/mmu.c\n@@ -127,7 +127,7 @@ bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,\n if (likely(excp == 0)) {\n tlb_set_page(cs, addr & TARGET_PAGE_MASK,\n phys_addr & TARGET_PAGE_MASK, prot,\n- mmu_idx, TARGET_PAGE_SIZE);\n+ access_type, mmu_idx, TARGET_PAGE_SIZE);\n return true;\n }\n if (probe) {\ndiff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c\nindex ac607054027..8b55a9e4ddf 100644\n--- a/target/ppc/mmu_helper.c\n+++ b/target/ppc/mmu_helper.c\n@@ -1369,7 +1369,7 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr eaddr, int size,\n if (ppc_xlate(cpu, eaddr, access_type, &raddr,\n &page_size, &prot, mmu_idx, !probe)) {\n tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,\n- prot, mmu_idx, 1UL << page_size);\n+ prot, access_type, mmu_idx, 1UL << page_size);\n return true;\n }\n if (probe) {\ndiff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c\nindex dd6c861a90e..ee0292e3423 100644\n--- a/target/riscv/cpu_helper.c\n+++ b/target/riscv/cpu_helper.c\n@@ -1874,7 +1874,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n \n if (ret == TRANSLATE_SUCCESS) {\n tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1),\n- prot, mmu_idx, tlb_size);\n+ prot, access_type, mmu_idx, tlb_size);\n return true;\n } else if (probe) {\n return false;\ndiff --git a/target/rx/cpu.c b/target/rx/cpu.c\nindex b5284199e6d..6114e345e65 100644\n--- a/target/rx/cpu.c\n+++ b/target/rx/cpu.c\n@@ -194,7 +194,8 @@ static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,\n /* Linear mapping */\n address = physical = addr & TARGET_PAGE_MASK;\n prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;\n- tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);\n+ tlb_set_page(cs, address, physical, prot, access_type,\n+ mmu_idx, TARGET_PAGE_SIZE);\n return true;\n }\n \ndiff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c\nindex 41b0017d767..6d89a8c328e 100644\n--- a/target/s390x/tcg/excp_helper.c\n+++ b/target/s390x/tcg/excp_helper.c\n@@ -182,7 +182,7 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n \"%s: set tlb %\" PRIx64 \" -> %\" PRIx64 \" (%x)\\n\",\n __func__, (uint64_t)vaddr, (uint64_t)raddr, prot);\n tlb_set_page(cs, address & TARGET_PAGE_MASK, raddr, prot,\n- mmu_idx, TARGET_PAGE_SIZE);\n+ access_type, mmu_idx, TARGET_PAGE_SIZE);\n return true;\n }\n if (probe) {\ndiff --git a/target/sh4/helper.c b/target/sh4/helper.c\nindex 5d6295618f5..2542d3d88f5 100644\n--- a/target/sh4/helper.c\n+++ b/target/sh4/helper.c\n@@ -812,7 +812,8 @@ bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n if (ret == MMU_OK) {\n address &= TARGET_PAGE_MASK;\n physical &= TARGET_PAGE_MASK;\n- tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);\n+ tlb_set_page(cs, address, physical, prot, access_type, mmu_idx,\n+ TARGET_PAGE_SIZE);\n return true;\n }\n if (probe) {\ndiff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c\nindex a6f76a1ab76..316f4182848 100644\n--- a/target/sparc/mmu_helper.c\n+++ b/target/sparc/mmu_helper.c\n@@ -236,7 +236,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n \"Translate at %\" VADDR_PRIx \" -> \"\n HWADDR_FMT_plx \", vaddr \" TARGET_FMT_lx \"\\n\",\n address, full.phys_addr, vaddr);\n- tlb_set_page_full(cs, mmu_idx, vaddr, &full);\n+ tlb_set_page_full(cs, mmu_idx, vaddr, access_type, &full);\n return true;\n }\n \n@@ -252,7 +252,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n neverland. Fake/overridden mappings will be flushed when\n switching to normal mode. */\n full.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;\n- tlb_set_page_full(cs, mmu_idx, vaddr, &full);\n+ tlb_set_page_full(cs, mmu_idx, vaddr, access_type, &full);\n return true;\n } else {\n if (access_type == MMU_INST_FETCH) {\n@@ -777,7 +777,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n trace_mmu_helper_mmu_fault(address, full.phys_addr, mmu_idx, env->tl,\n env->dmmu.mmu_primary_context,\n env->dmmu.mmu_secondary_context);\n- tlb_set_page_full(cs, mmu_idx, address, &full);\n+ tlb_set_page_full(cs, mmu_idx, address, access_type, &full);\n return true;\n }\n if (probe) {\ndiff --git a/target/tricore/helper.c b/target/tricore/helper.c\nindex 7ee8c7fd699..a7173dc73f0 100644\n--- a/target/tricore/helper.c\n+++ b/target/tricore/helper.c\n@@ -86,7 +86,7 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n if (ret == TLBRET_MATCH) {\n tlb_set_page(cs, address & TARGET_PAGE_MASK,\n physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,\n- mmu_idx, TARGET_PAGE_SIZE);\n+ rw, mmu_idx, TARGET_PAGE_SIZE);\n return true;\n } else {\n assert(ret < 0);\ndiff --git a/target/xtensa/helper.c b/target/xtensa/helper.c\nindex 2d93b45036d..2cd51ba0cb7 100644\n--- a/target/xtensa/helper.c\n+++ b/target/xtensa/helper.c\n@@ -282,7 +282,8 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,\n tlb_set_page(cs,\n address & TARGET_PAGE_MASK,\n paddr & TARGET_PAGE_MASK,\n- access, mmu_idx, page_size);\n+ access, access_type, mmu_idx,\n+ page_size);\n return true;\n } else if (probe) {\n return false;\n","prefixes":["v2","1/5"]}