{"id":2225777,"url":"http://patchwork.ozlabs.org/api/patches/2225777/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260421-io_projection-v2-1-4c251c692ef4@garyguo.net/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421-io_projection-v2-1-4c251c692ef4@garyguo.net>","list_archive_url":null,"date":"2026-04-21T14:56:12","name":"[v2,01/11] rust: io: generalize `MmioRaw` to pointer to arbitrary type","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"016921a076cc833e87ab99e707ba8ff1627406c3","submitter":{"id":76823,"url":"http://patchwork.ozlabs.org/api/people/76823/?format=json","name":"Gary Guo","email":"gary@garyguo.net"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260421-io_projection-v2-1-4c251c692ef4@garyguo.net/mbox/","series":[{"id":500833,"url":"http://patchwork.ozlabs.org/api/series/500833/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=500833","date":"2026-04-21T14:56:19","name":"rust: I/O type generalization and projection","version":2,"mbox":"http://patchwork.ozlabs.org/series/500833/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225777/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225777/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=garyguo.net header.i=@garyguo.net header.a=rsa-sha256\n header.s=selector1 header.b=VqbSJBQI;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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4fe97c69-24bd-4ecd-b278-08de9fb62a24","X-MS-Exchange-CrossTenant-AuthSource":"LOVP265MB8871.GBRP265.PROD.OUTLOOK.COM","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"21 Apr 2026 14:56:27.3841\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"bbc898ad-b10f-4e10-8552-d9377b823d45","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n VAOCeFOaBsvJtMWVG/hLi7gEv+m/cJdRJmxZ5chFbv59HHBvFBVRIM0U+nEraD/YAFLGMPADWMU5752fRcG6jA==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CWLP265MB5523"},"content":"Conceptually, `MmioRaw` is just `__iomem *`, so it should work for any\ntypes. The existing use case where it represents a region of compile-time\nknown minimum size and run-time known actual size is moved to a custom\ndynamic-sized type `Region` instead. The `maxsize` method is also\nrenamed to `size` to reflect that it is the actual size (not a bound) of\nthe region.\n\nSigned-off-by: Gary Guo \n---\n rust/kernel/devres.rs | 7 +++--\n rust/kernel/io.rs | 84 ++++++++++++++++++++++++++++++++++++++++-----------\n rust/kernel/io/mem.rs | 4 +--\n rust/kernel/pci/io.rs | 4 +--\n 4 files changed, 74 insertions(+), 25 deletions(-)","diff":"diff --git a/rust/kernel/devres.rs b/rust/kernel/devres.rs\nindex 9e5f93aed20c..65a4082122af 100644\n--- a/rust/kernel/devres.rs\n+++ b/rust/kernel/devres.rs\n@@ -71,14 +71,15 @@ struct Inner {\n /// IoKnownSize,\n /// Mmio,\n /// MmioRaw,\n-/// PhysAddr, //\n+/// PhysAddr,\n+/// Region, //\n /// },\n /// prelude::*,\n /// };\n /// use core::ops::Deref;\n ///\n /// // See also [`pci::Bar`] for a real example.\n-/// struct IoMem(MmioRaw);\n+/// struct IoMem(MmioRaw>);\n ///\n /// impl IoMem {\n /// /// # Safety\n@@ -93,7 +94,7 @@ struct Inner {\n /// return Err(ENOMEM);\n /// }\n ///\n-/// Ok(IoMem(MmioRaw::new(addr as usize, SIZE)?))\n+/// Ok(IoMem(MmioRaw::new_region(addr as usize, SIZE)?))\n /// }\n /// }\n ///\ndiff --git a/rust/kernel/io.rs b/rust/kernel/io.rs\nindex fcc7678fd9e3..d7f2145fa9b9 100644\n--- a/rust/kernel/io.rs\n+++ b/rust/kernel/io.rs\n@@ -6,7 +6,8 @@\n \n use crate::{\n bindings,\n- prelude::*, //\n+ prelude::*,\n+ ptr::KnownSize, //\n };\n \n pub mod mem;\n@@ -31,39 +32,85 @@\n /// `CONFIG_PHYS_ADDR_T_64BIT`, and it can be a u64 even on 32-bit architectures.\n pub type ResourceSize = bindings::resource_size_t;\n \n+/// Untyped I/O region.\n+///\n+/// This type can be used when an I/O region without known type information has a compile-time known\n+/// minimum size (and a runtime known actual size).\n+///\n+/// The `SIZE` generic parameter indicate the minimum size of the region.\n+#[repr(transparent)]\n+pub struct Region {\n+ inner: [u8],\n+}\n+\n+impl KnownSize for Region {\n+ #[inline(always)]\n+ fn size(p: *const Self) -> usize {\n+ (p as *const [u8]).len()\n+ }\n+}\n+\n /// Raw representation of an MMIO region.\n ///\n+/// `MmioRaw` is equivalent to `T __iomem *` in C.\n+///\n /// By itself, the existence of an instance of this structure does not provide any guarantees that\n /// the represented MMIO region does exist or is properly mapped.\n ///\n /// Instead, the bus specific MMIO implementation must convert this raw representation into an\n /// `Mmio` instance providing the actual memory accessors. Only by the conversion into an `Mmio`\n /// structure any guarantees are given.\n-pub struct MmioRaw {\n- addr: usize,\n- maxsize: usize,\n+pub struct MmioRaw {\n+ /// Pointer is in I/O address space.\n+ ///\n+ /// The provenance does not matter, only the address and metadata do.\n+ addr: *mut T,\n }\n \n-impl MmioRaw {\n- /// Returns a new `MmioRaw` instance on success, an error otherwise.\n- pub fn new(addr: usize, maxsize: usize) -> Result {\n- if maxsize < SIZE {\n+// SAFETY: `MmioRaw` is just an address, so is thread-safe.\n+unsafe impl Send for MmioRaw {}\n+// SAFETY: `MmioRaw` is just an address, so is thread-safe.\n+unsafe impl Sync for MmioRaw {}\n+\n+impl MmioRaw {\n+ /// Create a `MmioRaw` from address.\n+ #[inline]\n+ pub fn new(addr: usize) -> Self {\n+ Self {\n+ addr: core::ptr::without_provenance_mut(addr),\n+ }\n+ }\n+}\n+\n+impl MmioRaw> {\n+ /// Create a `MmioRaw` representing a I/O region with given size.\n+ ///\n+ /// The size is checked against the minimum size specified via const generics.\n+ #[inline]\n+ pub fn new_region(addr: usize, size: usize) -> Result {\n+ if size < SIZE {\n return Err(EINVAL);\n }\n \n- Ok(Self { addr, maxsize })\n+ let addr = core::ptr::slice_from_raw_parts_mut::(\n+ core::ptr::without_provenance_mut(addr),\n+ size,\n+ ) as *mut Region;\n+ Ok(Self { addr })\n }\n+}\n \n+impl MmioRaw {\n /// Returns the base address of the MMIO region.\n #[inline]\n pub fn addr(&self) -> usize {\n- self.addr\n+ self.addr.addr()\n }\n \n- /// Returns the maximum size of the MMIO region.\n+ /// Returns the size of the MMIO region.\n #[inline]\n- pub fn maxsize(&self) -> usize {\n- self.maxsize\n+ pub fn size(&self) -> usize {\n+ KnownSize::size(self.addr)\n }\n }\n \n@@ -89,12 +136,13 @@ pub fn maxsize(&self) -> usize {\n /// Mmio,\n /// MmioRaw,\n /// PhysAddr,\n+/// Region,\n /// },\n /// };\n /// use core::ops::Deref;\n ///\n /// // See also `pci::Bar` for a real example.\n-/// struct IoMem(MmioRaw);\n+/// struct IoMem(MmioRaw>);\n ///\n /// impl IoMem {\n /// /// # Safety\n@@ -109,7 +157,7 @@ pub fn maxsize(&self) -> usize {\n /// return Err(ENOMEM);\n /// }\n ///\n-/// Ok(IoMem(MmioRaw::new(addr as usize, SIZE)?))\n+/// Ok(IoMem(MmioRaw::new_region(addr as usize, SIZE)?))\n /// }\n /// }\n ///\n@@ -139,7 +187,7 @@ pub fn maxsize(&self) -> usize {\n /// # }\n /// ```\n #[repr(transparent)]\n-pub struct Mmio(MmioRaw);\n+pub struct Mmio(MmioRaw>);\n \n /// Checks whether an access of type `U` at the given `offset`\n /// is valid within this region.\n@@ -767,7 +815,7 @@ fn addr(&self) -> usize {\n /// Returns the maximum size of this mapping.\n #[inline]\n fn maxsize(&self) -> usize {\n- self.0.maxsize()\n+ self.0.size()\n }\n }\n \n@@ -782,7 +830,7 @@ impl Mmio {\n ///\n /// Callers must ensure that `addr` is the start of a valid I/O mapped memory region of size\n /// `maxsize`.\n- pub unsafe fn from_raw(raw: &MmioRaw) -> &Self {\n+ pub unsafe fn from_raw(raw: &MmioRaw>) -> &Self {\n // SAFETY: `Mmio` is a transparent wrapper around `MmioRaw`.\n unsafe { &*core::ptr::from_ref(raw).cast() }\n }\ndiff --git a/rust/kernel/io/mem.rs b/rust/kernel/io/mem.rs\nindex 7dc78d547f7a..9117d417f99c 100644\n--- a/rust/kernel/io/mem.rs\n+++ b/rust/kernel/io/mem.rs\n@@ -231,7 +231,7 @@ fn deref(&self) -> &Self::Target {\n /// [`IoMem`] always holds an [`MmioRaw`] instance that holds a valid pointer to the\n /// start of the I/O memory mapped region.\n pub struct IoMem {\n- io: MmioRaw,\n+ io: MmioRaw>,\n }\n \n impl IoMem {\n@@ -266,7 +266,7 @@ fn ioremap(resource: &Resource) -> Result {\n return Err(ENOMEM);\n }\n \n- let io = MmioRaw::new(addr as usize, size)?;\n+ let io = MmioRaw::new_region(addr as usize, size)?;\n let io = IoMem { io };\n \n Ok(io)\ndiff --git a/rust/kernel/pci/io.rs b/rust/kernel/pci/io.rs\nindex ae78676c927f..0335b5068f69 100644\n--- a/rust/kernel/pci/io.rs\n+++ b/rust/kernel/pci/io.rs\n@@ -148,7 +148,7 @@ impl<'a, S: ConfigSpaceKind> IoKnownSize for ConfigSpace<'a, S> {\n /// memory mapped PCI BAR and its size.\n pub struct Bar {\n pdev: ARef,\n- io: MmioRaw,\n+ io: MmioRaw>,\n num: i32,\n }\n \n@@ -184,7 +184,7 @@ pub(super) fn new(pdev: &Device, num: u32, name: &CStr) -> Result {\n return Err(ENOMEM);\n }\n \n- let io = match MmioRaw::new(ioptr, len as usize) {\n+ let io = match MmioRaw::new_region(ioptr, len as usize) {\n Ok(io) => io,\n Err(err) => {\n // SAFETY:\n","prefixes":["v2","01/11"]}