{"id":2225686,"url":"http://patchwork.ozlabs.org/api/patches/2225686/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260421-imx8mq-dm-pmic-v1-9-0e2b490542b1@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421-imx8mq-dm-pmic-v1-9-0e2b490542b1@nxp.com>","list_archive_url":null,"date":"2026-04-21T13:41:21","name":"[09/15] board: nxp: common: fix PFUZE100 DM build and unify DM/non-DM handling","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"5f5e8b80f54877f3420a8dea3ff569bed4eced41","submitter":{"id":80723,"url":"http://patchwork.ozlabs.org/api/people/80723/?format=json","name":"Peng Fan","email":"peng.fan@oss.nxp.com"},"delegate":{"id":151988,"url":"http://patchwork.ozlabs.org/api/users/151988/?format=json","username":"festevam","first_name":"Fabio","last_name":"Estevam","email":"festevam@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260421-imx8mq-dm-pmic-v1-9-0e2b490542b1@nxp.com/mbox/","series":[{"id":500790,"url":"http://patchwork.ozlabs.org/api/series/500790/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=500790","date":"2026-04-21T13:41:12","name":"i.MX8MQ: Convert to DM_PMIC for a few boards","version":1,"mbox":"http://patchwork.ozlabs.org/series/500790/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225686/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225686/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector1-NXP1-onmicrosoft-com\n header.b=KJ1F5s/4;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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phobos.denx.de","X-Virus-Status":"Clean"},"content":"From: Peng Fan \n\nSwitch PFUZE100 object linkage to be phase-aware and fix build issues\nwhen using driver model PMIC support.\n\nThe PFUZE100 helper code is reworked to:\n- Build pfuze.o only when CONFIG_(SPL_)DM_PMIC_PFUZE100 is enabled\n- Use CONFIG_IS_ENABLED(DM_PMIC_PFUZE100) for proper DM/non-DM selection\n- Align function signatures and implementations with DM PMIC APIs\n- Use udevice-based pmic access for DM and legacy pmic for non-DM\n- Avoid mixing struct pmic and struct udevice in the same build\n configuration\n\nNo functional change intended beyond fixing DM support and build\nconsistency.\n\nSigned-off-by: Peng Fan \n---\n board/nxp/common/Makefile | 2 +-\n board/nxp/common/pfuze.c | 96 +++++++++++++++++++++++------------------------\n board/nxp/common/pfuze.h | 2 +-\n 3 files changed, 50 insertions(+), 50 deletions(-)","diff":"diff --git a/board/nxp/common/Makefile b/board/nxp/common/Makefile\nindex ed102ae7bf7..dafd3717948 100644\n--- a/board/nxp/common/Makefile\n+++ b/board/nxp/common/Makefile\n@@ -57,7 +57,7 @@ obj-$(CONFIG_TARGET_P5040DS)\t\t+= ics307_clk.o\n ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y)\n obj-$(CONFIG_POWER_PFUZE100)\t+= pfuze.o\n endif\n-obj-$(CONFIG_DM_PMIC_PFUZE100)\t+= pfuze.o\n+obj-$(CONFIG_$(PHASE_)DM_PMIC_PFUZE100)\t+= pfuze.o\n obj-$(CONFIG_POWER_MC34VR500)\t+= mc34vr500.o\n ifneq (,$(filter $(SOC), imx8m imx8ulp imx9))\n obj-y\t\t\t\t+= mmc.o\ndiff --git a/board/nxp/common/pfuze.c b/board/nxp/common/pfuze.c\nindex 0d7a94fd232..179cc605da0 100644\n--- a/board/nxp/common/pfuze.c\n+++ b/board/nxp/common/pfuze.c\n@@ -7,14 +7,14 @@\n #include \n #include \n \n-#ifndef CONFIG_DM_PMIC_PFUZE100\n-int pfuze_mode_init(struct pmic *p, u32 mode)\n+#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100)\n+int pfuze_mode_init(struct udevice *dev, u32 mode)\n {\n \tunsigned char offset, i, switch_num;\n \tu32 id;\n \tint ret;\n \n-\tpmic_reg_read(p, PFUZE100_DEVICEID, &id);\n+\tid = pmic_reg_read(dev, PFUZE100_DEVICEID);\n \tid = id & 0xf;\n \n \tif (id == 0) {\n@@ -28,14 +28,14 @@ int pfuze_mode_init(struct pmic *p, u32 mode)\n \t\treturn -EINVAL;\n \t}\n \n-\tret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);\n+\tret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);\n \tif (ret < 0) {\n \t\tprintf(\"Set SW1AB mode error!\\n\");\n \t\treturn ret;\n \t}\n \n \tfor (i = 0; i < switch_num - 1; i++) {\n-\t\tret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);\n+\t\tret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);\n \t\tif (ret < 0) {\n \t\t\tprintf(\"Set switch 0x%x mode error!\\n\",\n \t\t\t offset + i * SWITCH_SIZE);\n@@ -46,58 +46,54 @@ int pfuze_mode_init(struct pmic *p, u32 mode)\n \treturn ret;\n }\n \n-struct pmic *pfuze_common_init(unsigned char i2cbus)\n+struct udevice *pfuze_common_init(void)\n {\n-\tstruct pmic *p;\n+\tstruct udevice *dev;\n \tint ret;\n-\tunsigned int reg;\n-\n-\tret = power_pfuze100_init(i2cbus);\n-\tif (ret)\n-\t\treturn NULL;\n+\tunsigned int reg, dev_id, rev_id;\n \n-\tp = pmic_get(\"PFUZE100\");\n-\tret = pmic_probe(p);\n-\tif (ret)\n+\tret = pmic_get(\"pfuze100@8\", &dev);\n+\tif (ret == -ENODEV)\n \t\treturn NULL;\n \n-\tpmic_reg_read(p, PFUZE100_DEVICEID, ®);\n-\tprintf(\"PMIC: PFUZE100 ID=0x%02x\\n\", reg);\n+\tdev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);\n+\trev_id = pmic_reg_read(dev, PFUZE100_REVID);\n+\tprintf(\"PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\\n\", dev_id, rev_id);\n \n \t/* Set SW1AB stanby volage to 0.975V */\n-\tpmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);\n+\treg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);\n \treg &= ~SW1x_STBY_MASK;\n \treg |= SW1x_0_975V;\n-\tpmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);\n+\tpmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);\n \n \t/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */\n-\tpmic_reg_read(p, PFUZE100_SW1ABCONF, ®);\n+\treg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);\n \treg &= ~SW1xCONF_DVSSPEED_MASK;\n \treg |= SW1xCONF_DVSSPEED_4US;\n-\tpmic_reg_write(p, PFUZE100_SW1ABCONF, reg);\n+\tpmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);\n \n \t/* Set SW1C standby voltage to 0.975V */\n-\tpmic_reg_read(p, PFUZE100_SW1CSTBY, ®);\n+\treg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);\n \treg &= ~SW1x_STBY_MASK;\n \treg |= SW1x_0_975V;\n-\tpmic_reg_write(p, PFUZE100_SW1CSTBY, reg);\n+\tpmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);\n \n \t/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */\n-\tpmic_reg_read(p, PFUZE100_SW1CCONF, ®);\n+\treg = pmic_reg_read(dev, PFUZE100_SW1CCONF);\n \treg &= ~SW1xCONF_DVSSPEED_MASK;\n \treg |= SW1xCONF_DVSSPEED_4US;\n-\tpmic_reg_write(p, PFUZE100_SW1CCONF, reg);\n+\tpmic_reg_write(dev, PFUZE100_SW1CCONF, reg);\n \n-\treturn p;\n+\treturn dev;\n }\n-#elif defined(CONFIG_DM_PMIC)\n-int pfuze_mode_init(struct udevice *dev, u32 mode)\n+#else\n+int pfuze_mode_init(struct pmic *p, u32 mode)\n {\n \tunsigned char offset, i, switch_num;\n \tu32 id;\n \tint ret;\n \n-\tid = pmic_reg_read(dev, PFUZE100_DEVICEID);\n+\tpmic_reg_read(p, PFUZE100_DEVICEID, &id);\n \tid = id & 0xf;\n \n \tif (id == 0) {\n@@ -111,14 +107,14 @@ int pfuze_mode_init(struct udevice *dev, u32 mode)\n \t\treturn -EINVAL;\n \t}\n \n-\tret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);\n+\tret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);\n \tif (ret < 0) {\n \t\tprintf(\"Set SW1AB mode error!\\n\");\n \t\treturn ret;\n \t}\n \n \tfor (i = 0; i < switch_num - 1; i++) {\n-\t\tret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);\n+\t\tret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);\n \t\tif (ret < 0) {\n \t\t\tprintf(\"Set switch 0x%x mode error!\\n\",\n \t\t\t offset + i * SWITCH_SIZE);\n@@ -129,44 +125,48 @@ int pfuze_mode_init(struct udevice *dev, u32 mode)\n \treturn ret;\n }\n \n-struct udevice *pfuze_common_init(void)\n+struct pmic *pfuze_common_init(unsigned char i2cbus)\n {\n-\tstruct udevice *dev;\n+\tstruct pmic *p;\n \tint ret;\n-\tunsigned int reg, dev_id, rev_id;\n+\tunsigned int reg;\n \n-\tret = pmic_get(\"pfuze100@8\", &dev);\n-\tif (ret == -ENODEV)\n+\tret = power_pfuze100_init(i2cbus);\n+\tif (ret)\n \t\treturn NULL;\n \n-\tdev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);\n-\trev_id = pmic_reg_read(dev, PFUZE100_REVID);\n-\tprintf(\"PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\\n\", dev_id, rev_id);\n+\tp = pmic_get(\"PFUZE100\");\n+\tret = pmic_probe(p);\n+\tif (ret)\n+\t\treturn NULL;\n+\n+\tpmic_reg_read(p, PFUZE100_DEVICEID, ®);\n+\tprintf(\"PMIC: PFUZE100 ID=0x%02x\\n\", reg);\n \n \t/* Set SW1AB stanby volage to 0.975V */\n-\treg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);\n+\tpmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);\n \treg &= ~SW1x_STBY_MASK;\n \treg |= SW1x_0_975V;\n-\tpmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);\n+\tpmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);\n \n \t/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */\n-\treg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);\n+\tpmic_reg_read(p, PFUZE100_SW1ABCONF, ®);\n \treg &= ~SW1xCONF_DVSSPEED_MASK;\n \treg |= SW1xCONF_DVSSPEED_4US;\n-\tpmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);\n+\tpmic_reg_write(p, PFUZE100_SW1ABCONF, reg);\n \n \t/* Set SW1C standby voltage to 0.975V */\n-\treg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);\n+\tpmic_reg_read(p, PFUZE100_SW1CSTBY, ®);\n \treg &= ~SW1x_STBY_MASK;\n \treg |= SW1x_0_975V;\n-\tpmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);\n+\tpmic_reg_write(p, PFUZE100_SW1CSTBY, reg);\n \n \t/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */\n-\treg = pmic_reg_read(dev, PFUZE100_SW1CCONF);\n+\tpmic_reg_read(p, PFUZE100_SW1CCONF, ®);\n \treg &= ~SW1xCONF_DVSSPEED_MASK;\n \treg |= SW1xCONF_DVSSPEED_4US;\n-\tpmic_reg_write(dev, PFUZE100_SW1CCONF, reg);\n+\tpmic_reg_write(p, PFUZE100_SW1CCONF, reg);\n \n-\treturn dev;\n+\treturn p;\n }\n #endif\ndiff --git a/board/nxp/common/pfuze.h b/board/nxp/common/pfuze.h\nindex 45b49afaeb7..da89853bd20 100644\n--- a/board/nxp/common/pfuze.h\n+++ b/board/nxp/common/pfuze.h\n@@ -6,7 +6,7 @@\n #ifndef __PFUZE_BOARD_HELPER__\n #define __PFUZE_BOARD_HELPER__\n \n-#ifdef CONFIG_DM_PMIC_PFUZE100\n+#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100)\n struct udevice *pfuze_common_init(void);\n int pfuze_mode_init(struct udevice *dev, u32 mode);\n #else\n","prefixes":["09/15"]}