{"id":2225577,"url":"http://patchwork.ozlabs.org/api/patches/2225577/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421075906.2928317-3-frank.chang@sifive.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421075906.2928317-3-frank.chang@sifive.com>","list_archive_url":null,"date":"2026-04-21T07:59:06","name":"[v3,2/2] target/riscv: Update MISA.X for non-standard extensions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"535580aa8170807f80aedc101f5bd5eb26869a43","submitter":{"id":79604,"url":"http://patchwork.ozlabs.org/api/people/79604/?format=json","name":"Frank Chang","email":"frank.chang@sifive.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421075906.2928317-3-frank.chang@sifive.com/mbox/","series":[{"id":500755,"url":"http://patchwork.ozlabs.org/api/series/500755/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500755","date":"2026-04-21T07:59:04","name":"Set MISA.[C|X] based on the selected extensions","version":3,"mbox":"http://patchwork.ozlabs.org/series/500755/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225577/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225577/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=BfOZDaOH;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pg1-x531.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Frank Chang \n\nMISA.X is set if there are any non-standard extensions.\nWe should set MISA.X when any of the vendor extensions is enabled.\n\nSigned-off-by: Frank Chang \nReviewed-by: Max Chou \nReviewed-by: Daniel Henrique Barboza \n---\n target/riscv/cpu.h | 1 +\n target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++\n 2 files changed, 16 insertions(+)","diff":"diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 4c0676ed53b..175e877f90a 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -69,6 +69,7 @@ typedef struct CPUArchState CPURISCVState;\n #define RVH RV('H')\n #define RVG RV('G')\n #define RVB RV('B')\n+#define RVX RV('X')\n \n extern const uint32_t misa_bits[];\n const char *riscv_get_misa_ext_name(uint32_t bit);\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex 0f68560bac1..44d948b5dca 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -1194,6 +1194,20 @@ static void riscv_cpu_update_misa_c(RISCVCPU *cpu)\n }\n }\n \n+/* MISA.X is set when any of the non-standard extensions is enabled. */\n+static void riscv_cpu_update_misa_x(RISCVCPU *cpu)\n+{\n+ CPURISCVState *env = &cpu->env;\n+ const RISCVCPUMultiExtConfig *arr = riscv_cpu_vendor_exts;\n+\n+ for (int i = 0; arr[i].name != NULL; i++) {\n+ if (isa_ext_is_enabled(cpu, arr[i].offset)) {\n+ riscv_cpu_set_misa_ext(env, env->misa_ext | RVX);\n+ break;\n+ }\n+ }\n+}\n+\n void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)\n {\n CPURISCVState *env = &cpu->env;\n@@ -1202,6 +1216,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)\n riscv_cpu_init_implied_exts_rules();\n riscv_cpu_enable_implied_rules(cpu);\n riscv_cpu_update_misa_c(cpu);\n+ riscv_cpu_update_misa_x(cpu);\n \n riscv_cpu_validate_misa_priv(env, &local_err);\n if (local_err != NULL) {\n","prefixes":["v3","2/2"]}