{"id":2225563,"url":"http://patchwork.ozlabs.org/api/patches/2225563/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421074204.2908422-2-frank.chang@sifive.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421074204.2908422-2-frank.chang@sifive.com>","list_archive_url":null,"date":"2026-04-21T07:42:03","name":"[v2,1/2] target/riscv: Add the implied rule for G extension","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"7c7dc80e7c5052b0734aed0b1d4bece94665c32b","submitter":{"id":79604,"url":"http://patchwork.ozlabs.org/api/people/79604/?format=json","name":"Frank Chang","email":"frank.chang@sifive.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421074204.2908422-2-frank.chang@sifive.com/mbox/","series":[{"id":500751,"url":"http://patchwork.ozlabs.org/api/series/500751/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500751","date":"2026-04-21T07:42:02","name":"Add the implied rules for G and B extensions","version":2,"mbox":"http://patchwork.ozlabs.org/series/500751/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225563/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225563/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=jH2OJkeC;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pl1-x631.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Jim Shu \n\nAdd the missing implied rule from G to imafd_zicsr_zifencei.\nriscv_cpu_validate_g() is also removed as imafd_zicsr_zifencei\ncan be enabled by the implied rule.\n\nSigned-off-by: Jim Shu \nReviewed-by: Frank Chang \n---\n target/riscv/cpu.c | 14 +++++++++++-\n target/riscv/tcg/tcg-cpu.c | 44 --------------------------------------\n 2 files changed, 13 insertions(+), 45 deletions(-)","diff":"diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 72c6f4f0f14..7978b4fad43 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -2247,6 +2247,18 @@ static RISCVCPUImpliedExtsRule RVV_IMPLIED = {\n },\n };\n \n+static RISCVCPUImpliedExtsRule RVG_IMPLIED = {\n+ .is_misa = true,\n+ .ext = RVG,\n+ .implied_misa_exts = RVI | RVM | RVA | RVF | RVD,\n+ .implied_multi_exts = {\n+ CPU_CFG_OFFSET(ext_zicsr),\n+ CPU_CFG_OFFSET(ext_zifencei),\n+\n+ RISCV_IMPLIED_EXTS_RULE_END\n+ },\n+};\n+\n static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {\n .ext = CPU_CFG_OFFSET(ext_zcb),\n .implied_multi_exts = {\n@@ -2634,7 +2646,7 @@ static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED = {\n \n RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {\n &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,\n- &RVM_IMPLIED, &RVV_IMPLIED, NULL\n+ &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED, NULL\n };\n \n RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex f3f78088956..840ef82350d 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -532,46 +532,6 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)\n cpu->cfg.ext_ziccrse = cpu->cfg.has_priv_1_11;\n }\n \n-static void riscv_cpu_validate_g(RISCVCPU *cpu)\n-{\n- const char *warn_msg = \"RVG mandates disabled extension %s\";\n- uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD};\n- bool send_warn = cpu_misa_ext_is_user_set(RVG);\n-\n- for (int i = 0; i < ARRAY_SIZE(g_misa_bits); i++) {\n- uint32_t bit = g_misa_bits[i];\n-\n- if (riscv_has_ext(&cpu->env, bit)) {\n- continue;\n- }\n-\n- if (!cpu_misa_ext_is_user_set(bit)) {\n- riscv_cpu_write_misa_bit(cpu, bit, true);\n- continue;\n- }\n-\n- if (send_warn) {\n- warn_report(warn_msg, riscv_get_misa_ext_name(bit));\n- }\n- }\n-\n- if (!cpu->cfg.ext_zicsr) {\n- if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) {\n- cpu->cfg.ext_zicsr = true;\n- } else if (send_warn) {\n- warn_report(warn_msg, \"zicsr\");\n- }\n- }\n-\n- if (!cpu->cfg.ext_zifencei) {\n- if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) {\n- cpu->cfg.ext_zifencei = true;\n- } else if (send_warn) {\n- warn_report(warn_msg, \"zifencei\");\n- }\n- }\n-}\n-\n static void riscv_cpu_validate_b(RISCVCPU *cpu)\n {\n const char *warn_msg = \"RVB mandates disabled extension %s\";\n@@ -611,10 +571,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)\n CPURISCVState *env = &cpu->env;\n Error *local_err = NULL;\n \n- if (riscv_has_ext(env, RVG)) {\n- riscv_cpu_validate_g(cpu);\n- }\n-\n if (riscv_has_ext(env, RVB)) {\n riscv_cpu_validate_b(cpu);\n }\n","prefixes":["v2","1/2"]}