{"id":2225548,"url":"http://patchwork.ozlabs.org/api/patches/2225548/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421071107.2848439-1-frank.chang@sifive.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421071107.2848439-1-frank.chang@sifive.com>","list_archive_url":null,"date":"2026-04-21T07:11:07","name":"[v3] target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"729c0f4c7867151a2c99ffe6669baf0900491c69","submitter":{"id":79604,"url":"http://patchwork.ozlabs.org/api/people/79604/?format=json","name":"Frank Chang","email":"frank.chang@sifive.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421071107.2848439-1-frank.chang@sifive.com/mbox/","series":[{"id":500746,"url":"http://patchwork.ozlabs.org/api/series/500746/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500746","date":"2026-04-21T07:11:07","name":"[v3] target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer","version":3,"mbox":"http://patchwork.ozlabs.org/series/500746/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225548/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225548/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=gg8LFrYR;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::1033;\n envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1033.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Frank Chang \n\nUse designated initializers to initialize riscv_excp_names[] and\nriscv_intr_names[] so that we don't have to explicitly add \"reserved\"\nitems. Also, add the missing trap names: sw_check, hw_error,\nvirt_illegal_instruction, semihost, s_guest_external, and\ncounter_overflow.\n\nSigned-off-by: Frank Chang \nReviewed-by: Max Chou \nReviewed-by: Daniel Henrique Barboza \nReviewed-by: Nutty Liu \nReviewed-by: Philippe Mathieu-Daudé \n---\n target/riscv/cpu.c | 89 +++++++++++++++++++++++-----------------------\n 1 file changed, 45 insertions(+), 44 deletions(-)","diff":"diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 72c6f4f0f14..ce15a17c37d 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -328,60 +328,61 @@ const char * const riscv_rvv_regnames[] = {\n };\n \n static const char * const riscv_excp_names[] = {\n- \"misaligned_fetch\",\n- \"fault_fetch\",\n- \"illegal_instruction\",\n- \"breakpoint\",\n- \"misaligned_load\",\n- \"fault_load\",\n- \"misaligned_store\",\n- \"fault_store\",\n- \"user_ecall\",\n- \"supervisor_ecall\",\n- \"hypervisor_ecall\",\n- \"machine_ecall\",\n- \"exec_page_fault\",\n- \"load_page_fault\",\n- \"reserved\",\n- \"store_page_fault\",\n- \"double_trap\",\n- \"reserved\",\n- \"reserved\",\n- \"reserved\",\n- \"guest_exec_page_fault\",\n- \"guest_load_page_fault\",\n- \"reserved\",\n- \"guest_store_page_fault\",\n+ [RISCV_EXCP_INST_ADDR_MIS] = \"misaligned_fetch\",\n+ [RISCV_EXCP_INST_ACCESS_FAULT] = \"fault_fetch\",\n+ [RISCV_EXCP_ILLEGAL_INST] = \"illegal_instruction\",\n+ [RISCV_EXCP_BREAKPOINT] = \"breakpoint\",\n+ [RISCV_EXCP_LOAD_ADDR_MIS] = \"misaligned_load\",\n+ [RISCV_EXCP_LOAD_ACCESS_FAULT] = \"fault_load\",\n+ [RISCV_EXCP_STORE_AMO_ADDR_MIS] = \"misaligned_store\",\n+ [RISCV_EXCP_STORE_AMO_ACCESS_FAULT] = \"fault_store\",\n+ [RISCV_EXCP_U_ECALL] = \"user_ecall\",\n+ [RISCV_EXCP_S_ECALL] = \"supervisor_ecall\",\n+ [RISCV_EXCP_VS_ECALL] = \"hypervisor_ecall\",\n+ [RISCV_EXCP_M_ECALL] = \"machine_ecall\",\n+ [RISCV_EXCP_INST_PAGE_FAULT] = \"exec_page_fault\",\n+ [RISCV_EXCP_LOAD_PAGE_FAULT] = \"load_page_fault\",\n+ [RISCV_EXCP_STORE_PAGE_FAULT] = \"store_page_fault\",\n+ [RISCV_EXCP_DOUBLE_TRAP] = \"double_trap\",\n+ [RISCV_EXCP_SW_CHECK] = \"sw_check\",\n+ [RISCV_EXCP_HW_ERR] = \"hw_error\",\n+ [RISCV_EXCP_INST_GUEST_PAGE_FAULT] = \"guest_exec_page_fault\",\n+ [RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT] = \"guest_load_page_fault\",\n+ [RISCV_EXCP_VIRT_INSTRUCTION_FAULT] = \"virt_illegal_instruction\",\n+ [RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT] = \"guest_store_page_fault\",\n+ [RISCV_EXCP_SEMIHOST] = \"semihost\",\n };\n \n static const char * const riscv_intr_names[] = {\n- \"u_software\",\n- \"s_software\",\n- \"vs_software\",\n- \"m_software\",\n- \"u_timer\",\n- \"s_timer\",\n- \"vs_timer\",\n- \"m_timer\",\n- \"u_external\",\n- \"s_external\",\n- \"vs_external\",\n- \"m_external\",\n- \"reserved\",\n- \"reserved\",\n- \"reserved\",\n- \"reserved\"\n+ [IRQ_U_SOFT] = \"u_software\",\n+ [IRQ_S_SOFT] = \"s_software\",\n+ [IRQ_VS_SOFT] = \"vs_software\",\n+ [IRQ_M_SOFT] = \"m_software\",\n+ [IRQ_U_TIMER] = \"u_timer\",\n+ [IRQ_S_TIMER] = \"s_timer\",\n+ [IRQ_VS_TIMER] = \"vs_timer\",\n+ [IRQ_M_TIMER] = \"m_timer\",\n+ [IRQ_U_EXT] = \"u_external\",\n+ [IRQ_S_EXT] = \"s_external\",\n+ [IRQ_VS_EXT] = \"vs_external\",\n+ [IRQ_M_EXT] = \"m_external\",\n+ [IRQ_S_GEXT] = \"s_guest_external\",\n+ [IRQ_PMU_OVF] = \"counter_overflow\",\n };\n \n const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)\n {\n if (async) {\n- return (cause < ARRAY_SIZE(riscv_intr_names)) ?\n- riscv_intr_names[cause] : \"(unknown)\";\n+ if ((cause < ARRAY_SIZE(riscv_intr_names)) && riscv_intr_names[cause]) {\n+ return riscv_intr_names[cause];\n+ }\n } else {\n- return (cause < ARRAY_SIZE(riscv_excp_names)) ?\n- riscv_excp_names[cause] : \"(unknown)\";\n+ if ((cause < ARRAY_SIZE(riscv_excp_names)) && riscv_excp_names[cause]) {\n+ return riscv_excp_names[cause];\n+ }\n }\n+\n+ return \"(unknown)\";\n }\n \n void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)\n","prefixes":["v3"]}