{"id":2225497,"url":"http://patchwork.ozlabs.org/api/patches/2225497/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421053140.752059-5-joel@jms.id.au/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421053140.752059-5-joel@jms.id.au>","list_archive_url":null,"date":"2026-04-21T05:31:29","name":"[v3,04/13] hw/riscv/boot: Provide a simple halting payload","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d35c9e676966382ef502d015b8aaa8fcc3ab89ee","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/people/48628/?format=json","name":"Joel Stanley","email":"joel@jms.id.au"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421053140.752059-5-joel@jms.id.au/mbox/","series":[{"id":500733,"url":"http://patchwork.ozlabs.org/api/series/500733/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500733","date":"2026-04-21T05:31:26","name":"hw/riscv: Add the Tenstorrent Atlantis machine","version":3,"mbox":"http://patchwork.ozlabs.org/series/500733/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225497/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225497/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=O92i3bQT;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g09yF4Wtvz1yJG\n\tfor ; Tue, 21 Apr 2026 15:33:56 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wF3ji-0000Tb-Tn; Tue, 21 Apr 2026 01:33:27 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wF3jg-0000SF-JE\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:33:25 -0400","from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wF3jf-0004QO-0s\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:33:24 -0400","by mail-pj1-x102b.google.com with SMTP id\n 98e67ed59e1d1-35fc258aaa4so2359402a91.2\n for ; Mon, 20 Apr 2026 22:33:22 -0700 (PDT)","from donnager-debian.. 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helo=mail-pj1-x102b.google.com","X-Spam_score_int":"-16","X-Spam_score":"-1.7","X-Spam_bar":"-","X-Spam_report":"(-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001,\n FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Nicholas Piggin \n\nOpenSBI hangs before any console output if the domain init code sees the\nnext stage is not in an executable region.\n\nIf no kernel payload is provided to QEMU, the next stage address is\nNULL, and the riscv virt machine memory map ends up covering the 0\naddress with the catch all S-mode RWX region and so OpenSBI prints\nconsole messages and does not hang until the next stage boot.\n\nThe soon to be added Tenstorrent Atlantis board address map has RAM\nstarting at 0 and it loads OpenSBI there, so it is M-mode and not\naccessible by S-mode, tripping the early check and hang.\n\nAdd a helper to set up a simple payload that gets OpenSBI messages\nto console.\n\nSigned-off-by: Nicholas Piggin \nReviewed-by: Daniel Henrique Barboza \nSigned-off-by: Joel Stanley \n---\nv3: MachineState argument was unused\n---\n include/hw/riscv/boot.h | 1 +\n hw/riscv/boot.c | 20 ++++++++++++++++++++\n 2 files changed, 21 insertions(+)","diff":"diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h\nindex fb90bf12399e..a1eb377474b9 100644\n--- a/include/hw/riscv/boot.h\n+++ b/include/hw/riscv/boot.h\n@@ -78,6 +78,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts\n hwaddr rom_base, hwaddr rom_size,\n uint64_t kernel_entry,\n uint64_t fdt_load_addr);\n+void riscv_setup_halting_payload(RISCVBootInfo *info, hwaddr addr);\n void riscv_rom_copy_firmware_info(MachineState *machine,\n RISCVHartArrayState *harts,\n hwaddr rom_base,\ndiff --git a/hw/riscv/boot.c b/hw/riscv/boot.c\nindex 3ea95c175c14..3a97fd1441f7 100644\n--- a/hw/riscv/boot.c\n+++ b/hw/riscv/boot.c\n@@ -518,6 +518,26 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts\n kernel_entry);\n }\n \n+/* Simple payload so OpenSBI does not hang early with no output */\n+void riscv_setup_halting_payload(RISCVBootInfo *info, hwaddr addr)\n+{\n+ int i;\n+ uint32_t payload_vec[] = {\n+ 0x10500073, /* 1: wfi */\n+ 0xffdff06f, /* j 1b */\n+ };\n+ /* copy in the payload vector in little_endian byte order */\n+ for (i = 0; i < ARRAY_SIZE(payload_vec); i++) {\n+ payload_vec[i] = cpu_to_le32(payload_vec[i]);\n+ }\n+ rom_add_blob_fixed_as(\"mrom.payload\", payload_vec, sizeof(payload_vec),\n+ addr, &address_space_memory);\n+\n+ info->kernel_size = sizeof(payload_vec);\n+ info->image_low_addr = addr;\n+ info->image_high_addr = info->image_low_addr + info->kernel_size;\n+}\n+\n void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr)\n {\n CPUState *cs;\n","prefixes":["v3","04/13"]}