{"id":2225488,"url":"http://patchwork.ozlabs.org/api/patches/2225488/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mshv_accel_arm64_supp-v3-4-469f544778ba@linux.microsoft.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421-mshv_accel_arm64_supp-v3-4-469f544778ba@linux.microsoft.com>","list_archive_url":null,"date":"2026-04-21T05:21:49","name":"[v3,04/14] target/arm/mshv: implement vcpu state operations for ARM64","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"666c13137bcd2292b96769e737fc9f24ae1f201f","submitter":{"id":92925,"url":"http://patchwork.ozlabs.org/api/people/92925/?format=json","name":"Aastha Rawat","email":"aastharawat@linux.microsoft.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mshv_accel_arm64_supp-v3-4-469f544778ba@linux.microsoft.com/mbox/","series":[{"id":500731,"url":"http://patchwork.ozlabs.org/api/series/500731/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500731","date":"2026-04-21T05:21:47","name":"Add ARM64 support for MSHV accelerator","version":3,"mbox":"http://patchwork.ozlabs.org/series/500731/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225488/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225488/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=JeOXtF85;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1776748915;\n bh=aq6peFJqXAk4Wdw5L6TgML9sHcjISQM3jb5y79oWVCw=;\n h=From:Date:Subject:References:In-Reply-To:To:Cc:From;\n b=JeOXtF85II8AVIwZZ2MrMVDkWd+BzX24GDOQJiri4l3lGCaULNwB3mksg7Il00CKD\n O0S8xhghW4KmPJ2ff2foaFDR0HsxeAkBzLlnrgweAr+QtAIm/awaBJr8UL2dvTOH1I\n LlT3UR+L0VSVciy5TmVjjXhZeoTaB+XSc2qu/Fp8=","From":"Aastha Rawat ","Date":"Tue, 21 Apr 2026 05:21:49 +0000","Subject":"[PATCH v3 04/14] target/arm/mshv: implement vcpu state operations\n for ARM64","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"\n <20260421-mshv_accel_arm64_supp-v3-4-469f544778ba@linux.microsoft.com>","References":"\n <20260421-mshv_accel_arm64_supp-v3-0-469f544778ba@linux.microsoft.com>","In-Reply-To":"\n <20260421-mshv_accel_arm64_supp-v3-0-469f544778ba@linux.microsoft.com>","To":"qemu-devel@nongnu.org","Cc":"Magnus Kulke ,\n Wei Liu , Paolo Bonzini ,\n\t=?utf-8?q?Marc-Andr=C3=A9_Lureau?= ,\n\t=?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , =?utf-8?q?Phil?=\n\t=?utf-8?q?ippe_Mathieu-Daud=C3=A9?= ,\n Peter Maydell ,\n Anirudh Rayabharam ,\n Aastha Rawat ,\n Magnus Kulke , qemu-arm@nongnu.org,\n Alexander Graf , Pedro Barbuda ,\n Mohamed Mediouni ","X-Mailer":"b4 0.15.1","Received-SPF":"pass client-ip=13.77.154.182;\n envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com","X-Spam_score_int":"-42","X-Spam_score":"-4.3","X-Spam_bar":"----","X-Spam_report":"(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add support for reading and writing ARM64 CPU registers in the MSHV\naccelerator. This includes functions to set and get registers,\ninitialize and destroy VCPU state, and manage register state\nsynchronization between QEMU and hypervisor.\n\nSigned-off-by: Aastha Rawat \n---\n include/hw/hyperv/hvgdk_mini.h | 42 +++++++++++++\n target/arm/mshv/mshv-all.c | 138 +++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 180 insertions(+)","diff":"diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h\nindex cb52cc9de2..dfe94050f4 100644\n--- a/include/hw/hyperv/hvgdk_mini.h\n+++ b/include/hw/hyperv/hvgdk_mini.h\n@@ -13,6 +13,46 @@ typedef enum hv_register_name {\n /* Pending Interruption Register */\n HV_REGISTER_PENDING_INTERRUPTION = 0x00010002,\n \n+#if defined(__aarch64__)\n+ HV_ARM64_REGISTER_XZR = 0x0002FFFE,\n+ HV_ARM64_REGISTER_X0 = 0x00020000,\n+ HV_ARM64_REGISTER_X1 = 0x00020001,\n+ HV_ARM64_REGISTER_X2 = 0x00020002,\n+ HV_ARM64_REGISTER_X3 = 0x00020003,\n+ HV_ARM64_REGISTER_X4 = 0x00020004,\n+ HV_ARM64_REGISTER_X5 = 0x00020005,\n+ HV_ARM64_REGISTER_X6 = 0x00020006,\n+ HV_ARM64_REGISTER_X7 = 0x00020007,\n+ HV_ARM64_REGISTER_X8 = 0x00020008,\n+ HV_ARM64_REGISTER_X9 = 0x00020009,\n+ HV_ARM64_REGISTER_X10 = 0x0002000A,\n+ HV_ARM64_REGISTER_X11 = 0x0002000B,\n+ HV_ARM64_REGISTER_X12 = 0x0002000C,\n+ HV_ARM64_REGISTER_X13 = 0x0002000D,\n+ HV_ARM64_REGISTER_X14 = 0x0002000E,\n+ HV_ARM64_REGISTER_X15 = 0x0002000F,\n+ HV_ARM64_REGISTER_X16 = 0x00020010,\n+ HV_ARM64_REGISTER_X17 = 0x00020011,\n+ HV_ARM64_REGISTER_X18 = 0x00020012,\n+ HV_ARM64_REGISTER_X19 = 0x00020013,\n+ HV_ARM64_REGISTER_X20 = 0x00020014,\n+ HV_ARM64_REGISTER_X21 = 0x00020015,\n+ HV_ARM64_REGISTER_X22 = 0x00020016,\n+ HV_ARM64_REGISTER_X23 = 0x00020017,\n+ HV_ARM64_REGISTER_X24 = 0x00020018,\n+ HV_ARM64_REGISTER_X25 = 0x00020019,\n+ HV_ARM64_REGISTER_X26 = 0x0002001A,\n+ HV_ARM64_REGISTER_X27 = 0x0002001B,\n+ HV_ARM64_REGISTER_X28 = 0x0002001C,\n+ HV_ARM64_REGISTER_FP = 0x0002001D,\n+ HV_ARM64_REGISTER_LR = 0x0002001E,\n+ HV_ARM64_REGISTER_PC = 0x00020022,\n+\n+ /* AArch64 System Register Descriptions: General system control registers */\n+ HV_ARM64_REGISTER_MIDR_EL1 = 0x00040051,\n+ HV_ARM64_REGISTER_MPIDR_EL1 = 0x00040001,\n+\n+#elif defined(__x86_64__)\n /* X64 User-Mode Registers */\n HV_X64_REGISTER_RAX = 0x00020000,\n HV_X64_REGISTER_RCX = 0x00020001,\n@@ -157,6 +197,8 @@ typedef enum hv_register_name {\n /* Other MSRs */\n HV_X64_REGISTER_MSR_IA32_MISC_ENABLE = 0x000800A0,\n \n+#endif\n+\n /* Misc */\n HV_REGISTER_GUEST_OS_ID = 0x00090002,\n HV_REGISTER_REFERENCE_TSC = 0x00090017,\ndiff --git a/target/arm/mshv/mshv-all.c b/target/arm/mshv/mshv-all.c\nindex 1c82e2c593..ad9cb267a8 100644\n--- a/target/arm/mshv/mshv-all.c\n+++ b/target/arm/mshv/mshv-all.c\n@@ -9,16 +9,146 @@\n * SPDX-License-Identifier: GPL-2.0-or-later\n */\n \n+\n+#include \"qemu/osdep.h\"\n+#include \n+\n+#include \"qemu/error-report.h\"\n+#include \"qemu/memalign.h\"\n+\n+#include \"system/cpus.h\"\n+#include \"target/arm/cpu.h\"\n+\n #include \"system/mshv.h\"\n #include \"system/mshv_int.h\"\n+#include \"hw/hyperv/hvgdk_mini.h\"\n+\n+static enum hv_register_name STANDARD_REGISTER_NAMES[32] = {\n+ HV_ARM64_REGISTER_X0,\n+ HV_ARM64_REGISTER_X1,\n+ HV_ARM64_REGISTER_X2,\n+ HV_ARM64_REGISTER_X3,\n+ HV_ARM64_REGISTER_X4,\n+ HV_ARM64_REGISTER_X5,\n+ HV_ARM64_REGISTER_X6,\n+ HV_ARM64_REGISTER_X7,\n+ HV_ARM64_REGISTER_X8,\n+ HV_ARM64_REGISTER_X9,\n+ HV_ARM64_REGISTER_X10,\n+ HV_ARM64_REGISTER_X11,\n+ HV_ARM64_REGISTER_X12,\n+ HV_ARM64_REGISTER_X13,\n+ HV_ARM64_REGISTER_X14,\n+ HV_ARM64_REGISTER_X15,\n+ HV_ARM64_REGISTER_X16,\n+ HV_ARM64_REGISTER_X17,\n+ HV_ARM64_REGISTER_X18,\n+ HV_ARM64_REGISTER_X19,\n+ HV_ARM64_REGISTER_X20,\n+ HV_ARM64_REGISTER_X21,\n+ HV_ARM64_REGISTER_X22,\n+ HV_ARM64_REGISTER_X23,\n+ HV_ARM64_REGISTER_X24,\n+ HV_ARM64_REGISTER_X25,\n+ HV_ARM64_REGISTER_X26,\n+ HV_ARM64_REGISTER_X27,\n+ HV_ARM64_REGISTER_X28,\n+ HV_ARM64_REGISTER_FP,\n+ HV_ARM64_REGISTER_LR,\n+ HV_ARM64_REGISTER_PC,\n+};\n+\n+static int set_standard_regs(const CPUState *cpu)\n+{\n+ size_t n_regs = ARRAY_SIZE(STANDARD_REGISTER_NAMES);\n+ struct hv_register_assoc *assocs;\n+ int ret;\n+ ARMCPU *arm_cpu = ARM_CPU(cpu);\n+ CPUARMState *env = &arm_cpu->env;\n+\n+ assocs = g_new0(hv_register_assoc, n_regs);\n+\n+ for (size_t i = 0; i < n_regs - 1; i++) {\n+ assocs[i].name = STANDARD_REGISTER_NAMES[i];\n+ assocs[i].value.reg64 = env->xregs[i];\n+ }\n+\n+ /* Last register is the program counter */\n+ assocs[n_regs - 1].name = STANDARD_REGISTER_NAMES[n_regs - 1];\n+ assocs[n_regs - 1].value.reg64 = env->pc;\n+\n+ ret = mshv_set_generic_regs(cpu, assocs, n_regs);\n+ if (ret < 0) {\n+ error_report(\"failed to set standard registers\");\n+ g_free(assocs);\n+ return -1;\n+ }\n+\n+ g_free(assocs);\n+\n+ return 0;\n+}\n+\n+static void populate_standard_regs(const hv_register_assoc *assocs,\n+ CPUARMState *env)\n+{\n+ size_t n_regs = ARRAY_SIZE(STANDARD_REGISTER_NAMES);\n+\n+ for (size_t i = 0; i < n_regs - 1; i++) {\n+ env->xregs[i] = assocs[i].value.reg64;\n+ }\n+\n+ /* Last register is the program counter */\n+ env->pc = assocs[n_regs - 1].value.reg64;\n+}\n \n int mshv_load_regs(CPUState *cpu)\n {\n+ int ret;\n+\n+ ret = mshv_get_standard_regs(cpu);\n+ if (ret < 0) {\n+ error_report(\"Failed to load standard registers\");\n+ return -1;\n+ }\n+\n+ return 0;\n+}\n+\n+int mshv_get_standard_regs(CPUState *cpu)\n+{\n+ size_t n_regs = ARRAY_SIZE(STANDARD_REGISTER_NAMES);\n+ struct hv_register_assoc *assocs;\n+ int ret;\n+ ARMCPU *arm_cpu = ARM_CPU(cpu);\n+ CPUARMState *env = &arm_cpu->env;\n+\n+ assocs = g_new0(hv_register_assoc, n_regs);\n+ for (size_t i = 0; i < n_regs; i++) {\n+ assocs[i].name = STANDARD_REGISTER_NAMES[i];\n+ }\n+ ret = mshv_get_generic_regs(cpu, assocs, n_regs);\n+ if (ret < 0) {\n+ error_report(\"failed to get standard registers\");\n+ g_free(assocs);\n+ return -1;\n+ }\n+\n+ populate_standard_regs(assocs, env);\n+\n+ g_free(assocs);\n return 0;\n }\n \n int mshv_arch_put_registers(const CPUState *cpu)\n {\n+ int ret;\n+\n+ ret = set_standard_regs(cpu);\n+ if (ret < 0) {\n+ return ret;\n+ }\n+\n return 0;\n }\n \n@@ -29,12 +159,20 @@ int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message *msg, MshvVmExit *exit)\n \n void mshv_arch_init_vcpu(CPUState *cpu)\n {\n+ AccelCPUState *state = cpu->accel;\n \n+ mshv_setup_hvcall_args(state);\n }\n \n void mshv_arch_destroy_vcpu(CPUState *cpu)\n {\n+ AccelCPUState *state = cpu->accel;\n+\n+ if (state->hvcall_args.base) {\n+ qemu_vfree(state->hvcall_args.base);\n+ }\n \n+ state->hvcall_args = (MshvHvCallArgs){0};\n }\n \n void mshv_init_mmio_emu(void)\n","prefixes":["v3","04/14"]}