{"id":2225471,"url":"http://patchwork.ozlabs.org/api/patches/2225471/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421051346.41106-25-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421051346.41106-25-richard.henderson@linaro.org>","list_archive_url":null,"date":"2026-04-21T05:13:33","name":"[24/37] target/arm: Implement BF1CVT, BF1CVTLT, BF2CVT, BF2CVTLT for SVE","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"76c91b6e6db158d5a35af7d3ecbcaf5dde7895f8","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421051346.41106-25-richard.henderson@linaro.org/mbox/","series":[{"id":500729,"url":"http://patchwork.ozlabs.org/api/series/500729/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500729","date":"2026-04-21T05:13:11","name":"target/arm: Implement FEAT_FAMINMAX, FEAT_FPMR, FEAT_FP8","version":1,"mbox":"http://patchwork.ozlabs.org/series/500729/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225471/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225471/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=IZdQD3Ar;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g09dY5KMmz1yJG\n\tfor ; Tue, 21 Apr 2026 15:19:29 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wF3Ry-0008Iu-Pi; Tue, 21 Apr 2026 01:15:06 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wF3Rm-00087l-VI\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:14:56 -0400","from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wF3Rj-0006dO-4F\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:14:54 -0400","by mail-pj1-x1030.google.com with SMTP id\n 98e67ed59e1d1-35da9692ec3so3450913a91.1\n for ; Mon, 20 Apr 2026 22:14:50 -0700 (PDT)","from stoup.. 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helo=mail-pj1-x1030.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/cpu-features.h | 6 ++++++\n target/arm/tcg/helper-fp8-defs.h | 1 +\n target/arm/tcg/fp8_helper.c | 28 ++++++++++++++++++++++++++++\n target/arm/tcg/translate-sve.c | 23 +++++++++++++++++++++++\n target/arm/tcg/sve.decode | 6 ++++++\n 5 files changed, 64 insertions(+)","diff":"diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 8a6e5d555b..7f1a394ef0 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1624,6 +1624,12 @@ isar_feature_aa64_sme2_or_sve2_faminmax(const ARMISARegisters *id)\n return isar_feature_aa64_sme2_or_sve2(id) && isar_feature_aa64_faminmax(id);\n }\n \n+static inline bool\n+isar_feature_aa64_sme2_or_sve2_f8cvt(const ARMISARegisters *id)\n+{\n+ return isar_feature_aa64_sme2_or_sve2(id) && isar_feature_aa64_f8cvt(id);\n+}\n+\n /*\n * Feature tests for \"does this exist in either 32-bit or 64-bit?\"\n */\ndiff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex 0caaf63749..18ff483bb0 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -4,3 +4,4 @@\n */\n \n DEF_HELPER_FLAGS_4(advsimd_bfcvtl, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_4(sve2_bfcvt, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex a2efdd5cd7..b03345c670 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -121,3 +121,31 @@ void HELPER(advsimd_bfcvtl)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n fp8_finish(env, &ctx);\n clear_tail(vd, 16, simd_maxsz(desc));\n }\n+\n+void HELPER(sve2_bfcvt)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_src_start(env, desc, 0x3f);\n+ uint8_t *n = vn;\n+ uint16_t *d = vd;\n+ size_t nelem = simd_oprsz(desc) / 2;\n+\n+ switch (ctx.f8fmt) {\n+ case OFP8_E5M2:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e5m2 e = n[H1(2 * i + ctx.high)];\n+ d[H2(i)] = float8_e5m2_to_bfloat16(e, ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ case OFP8_E4M3:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e4m3 e = n[H1(2 * i + ctx.high)];\n+ d[H2(i)] = float8_e4m3_to_bfloat16(e, ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ default:\n+ bfloat16_invalid_input(d, nelem, &ctx.stat);\n+ break;\n+ }\n+\n+ fp8_finish(env, &ctx);\n+}\ndiff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c\nindex 756c4373b5..1540cbd6de 100644\n--- a/target/arm/tcg/translate-sve.c\n+++ b/target/arm/tcg/translate-sve.c\n@@ -21,6 +21,7 @@\n #include \"cpu.h\"\n #include \"helper-sme.h\"\n #include \"helper-sve.h\"\n+#include \"helper-fp8.h\"\n #include \"translate.h\"\n #include \"translate-a64.h\"\n #include \"fpu/softfloat.h\"\n@@ -4066,6 +4067,28 @@ TRANS_FEAT(FRSQRTE, aa64_sme_or_sve, gen_gvec_fpst_ah_arg_zz,\n s->fpcr_ah && dc_isar_feature(aa64_rpres, s) ?\n frsqrte_rpres_fns[a->esz] : frsqrte_fns[a->esz], a, 0)\n \n+static bool do_f8cvt(DisasContext *s, arg_rr_esz *a,\n+ gen_helper_gvec_2_ptr *fn, bool issrc2, bool isodd)\n+{\n+ if (fpmr_access_check(s) && sve_access_check(s)) {\n+ unsigned vsz = vec_full_reg_size(s);\n+ tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->rd),\n+ vec_full_reg_offset(s, a->rn),\n+ tcg_env, vsz, vsz,\n+ issrc2 | (isodd << 1) | (FPST_A64 << 2), fn);\n+ }\n+ return true;\n+}\n+\n+TRANS_FEAT(BF1CVT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n+ gen_helper_sve2_bfcvt, false, false)\n+TRANS_FEAT(BF2CVT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n+ gen_helper_sve2_bfcvt, true, false)\n+TRANS_FEAT(BF1CVTLT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n+ gen_helper_sve2_bfcvt, false, true)\n+TRANS_FEAT(BF2CVTLT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n+ gen_helper_sve2_bfcvt, true, true)\n+\n /*\n *** SVE Floating Point Compare with Zero Group\n */\ndiff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode\nindex 078a085a79..e7984fa8e0 100644\n--- a/target/arm/tcg/sve.decode\n+++ b/target/arm/tcg/sve.decode\n@@ -108,6 +108,7 @@\n # Two operand\n @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz\n @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz\n+@rd_rn_e0 ........ .. ...... ...... rn:5 rd:5 &rr_esz esz=0\n @rd_rnx2 ........ ... ..... ...... ..... rd:5 &rr_esz rn=%rn_ax2\n \n # Two operand with governing predicate, flags setting\n@@ -1090,6 +1091,11 @@ FMINQV 01100100 .. 010 111 101 ... ..... ..... @rd_pg_rn\n FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn\n FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn\n \n+BF1CVT 01100101 00 001 000 001110 ..... ..... @rd_rn_e0\n+BF2CVT 01100101 00 001 000 001111 ..... ..... @rd_rn_e0\n+BF1CVTLT 01100101 00 001 001 001110 ..... ..... @rd_rn_e0\n+BF2CVTLT 01100101 00 001 001 001111 ..... ..... @rd_rn_e0\n+\n ### SVE FP Compare with Zero Group\n \n FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn\n","prefixes":["24/37"]}