{"id":2225445,"url":"http://patchwork.ozlabs.org/api/patches/2225445/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421051346.41106-5-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421051346.41106-5-richard.henderson@linaro.org>","list_archive_url":null,"date":"2026-04-21T05:13:13","name":"[04/37] target/arm: Implement FEAT_FAMINMAX for SVE","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"bbbf0f9c1511fd920eebb8bcb990f1b360e2dda0","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421051346.41106-5-richard.henderson@linaro.org/mbox/","series":[{"id":500729,"url":"http://patchwork.ozlabs.org/api/series/500729/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500729","date":"2026-04-21T05:13:11","name":"target/arm: Implement FEAT_FAMINMAX, FEAT_FPMR, FEAT_FP8","version":1,"mbox":"http://patchwork.ozlabs.org/series/500729/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225445/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225445/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=yLHlW0Ej;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g09YR25GNz1yCv\n\tfor ; Tue, 21 Apr 2026 15:15:55 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wF3Rq-0008Bb-Rr; Tue, 21 Apr 2026 01:14:58 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wF3Qz-0007vz-5e\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:14:06 -0400","from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wF3Qx-0006Kp-Cu\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:14:04 -0400","by mail-pl1-x62d.google.com with SMTP id\n d9443c01a7336-2b23fcf90b2so37322185ad.3\n for ; Mon, 20 Apr 2026 22:14:02 -0700 (PDT)","from stoup.. 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","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/cpu-features.h | 11 +++++++++++\n target/arm/tcg/helper-sve-defs.h | 14 ++++++++++++++\n target/arm/tcg/sve_helper.c | 8 ++++++++\n target/arm/tcg/translate-sve.c | 2 ++\n target/arm/tcg/sve.decode | 2 ++\n 5 files changed, 37 insertions(+)","diff":"diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex a2ce38faa3..03631018d7 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1549,6 +1549,11 @@ static inline bool isar_feature_aa64_sme_or_sve2(const ARMISARegisters *id)\n return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2(id);\n }\n \n+static inline bool isar_feature_aa64_sme2_or_sve2(const ARMISARegisters *id)\n+{\n+ return isar_feature_aa64_sme2(id) || isar_feature_aa64_sve2(id);\n+}\n+\n static inline bool isar_feature_aa64_sme_or_sve2p1(const ARMISARegisters *id)\n {\n return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2p1(id);\n@@ -1589,6 +1594,12 @@ static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)\n return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_bf16(id);\n }\n \n+static inline bool\n+isar_feature_aa64_sme2_or_sve2_faminmax(const ARMISARegisters *id)\n+{\n+ return isar_feature_aa64_sme2_or_sve2(id) && isar_feature_aa64_faminmax(id);\n+}\n+\n /*\n * Feature tests for \"does this exist in either 32-bit or 64-bit?\"\n */\ndiff --git a/target/arm/tcg/helper-sve-defs.h b/target/arm/tcg/helper-sve-defs.h\nindex c3541a8ca8..1eebb64a29 100644\n--- a/target/arm/tcg/helper-sve-defs.h\n+++ b/target/arm/tcg/helper-sve-defs.h\n@@ -3166,3 +3166,17 @@ DEF_HELPER_FLAGS_5(sve2p1_st1ss_le_c, TCG_CALL_NO_WG, void, env, ptr, tl, i32, i\n DEF_HELPER_FLAGS_5(sve2p1_st1ss_be_c, TCG_CALL_NO_WG, void, env, ptr, tl, i32, i64)\n DEF_HELPER_FLAGS_5(sve2p1_st1dd_le_c, TCG_CALL_NO_WG, void, env, ptr, tl, i32, i64)\n DEF_HELPER_FLAGS_5(sve2p1_st1dd_be_c, TCG_CALL_NO_WG, void, env, ptr, tl, i32, i64)\n+\n+DEF_HELPER_FLAGS_6(sve2_famax_h, TCG_CALL_NO_RWG,\n+ void, ptr, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_6(sve2_famax_s, TCG_CALL_NO_RWG,\n+ void, ptr, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_6(sve2_famax_d, TCG_CALL_NO_RWG,\n+ void, ptr, ptr, ptr, ptr, fpst, i32)\n+\n+DEF_HELPER_FLAGS_6(sve2_famin_h, TCG_CALL_NO_RWG,\n+ void, ptr, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_6(sve2_famin_s, TCG_CALL_NO_RWG,\n+ void, ptr, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_6(sve2_famin_d, TCG_CALL_NO_RWG,\n+ void, ptr, ptr, ptr, ptr, fpst, i32)\ndiff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c\nindex 062d8881bd..9968600f75 100644\n--- a/target/arm/tcg/sve_helper.c\n+++ b/target/arm/tcg/sve_helper.c\n@@ -4742,6 +4742,14 @@ DO_ZPZZ_FP(sve_fmulx_h, uint16_t, H1_2, helper_advsimd_mulxh)\n DO_ZPZZ_FP(sve_fmulx_s, uint32_t, H1_4, helper_vfp_mulxs)\n DO_ZPZZ_FP(sve_fmulx_d, uint64_t, H1_8, helper_vfp_mulxd)\n \n+DO_ZPZZ_FP(sve2_famax_h, uint16_t, H1_2, float16_famax)\n+DO_ZPZZ_FP(sve2_famax_s, uint32_t, H1_4, float32_famax)\n+DO_ZPZZ_FP(sve2_famax_d, uint64_t, H1_8, float64_famax)\n+\n+DO_ZPZZ_FP(sve2_famin_h, uint16_t, H1_2, float16_famin)\n+DO_ZPZZ_FP(sve2_famin_s, uint32_t, H1_4, float32_famin)\n+DO_ZPZZ_FP(sve2_famin_d, uint64_t, H1_8, float64_famin)\n+\n #undef DO_ZPZZ_FP\n \n /* Three-operand expander, with one scalar operand, controlled by\ndiff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c\nindex 5bace3fda1..756c4373b5 100644\n--- a/target/arm/tcg/translate-sve.c\n+++ b/target/arm/tcg/translate-sve.c\n@@ -4252,6 +4252,8 @@ DO_ZPZZ_AH_FP(FABD, aa64_sme_or_sve, sve_fabd, sve_ah_fabd)\n DO_ZPZZ_FP(FSCALE, aa64_sme_or_sve, sve_fscalbn)\n DO_ZPZZ_FP(FDIV, aa64_sme_or_sve, sve_fdiv)\n DO_ZPZZ_FP(FMULX, aa64_sme_or_sve, sve_fmulx)\n+DO_ZPZZ_FP(FAMAX, aa64_sme2_or_sve2_faminmax, sve2_famax)\n+DO_ZPZZ_FP(FAMIN, aa64_sme2_or_sve2_faminmax, sve2_famin)\n \n typedef void gen_helper_sve_fp2scalar(TCGv_ptr, TCGv_ptr, TCGv_ptr,\n TCGv_i64, TCGv_ptr, TCGv_i32);\ndiff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode\nindex ab63cfaa0f..078a085a79 100644\n--- a/target/arm/tcg/sve.decode\n+++ b/target/arm/tcg/sve.decode\n@@ -1130,6 +1130,8 @@ FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm\n FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm\n FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR\n FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm\n+FAMAX 01100101 .. 00 1110 100 ... ..... ..... @rdn_pg_rm\n+FAMIN 01100101 .. 00 1111 100 ... ..... ..... @rdn_pg_rm\n \n # SVE floating-point arithmetic with immediate (predicated)\n FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1\n","prefixes":["04/37"]}