{"id":2225437,"url":"http://patchwork.ozlabs.org/api/patches/2225437/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260421-02-spi-fifo-reset-v1-1-e2cdd4bd474d@gentoo.org/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260421-02-spi-fifo-reset-v1-1-e2cdd4bd474d@gentoo.org>","list_archive_url":null,"date":"2026-04-21T04:47:50","name":"spi: sunxi: wait for TX/RX fifo reset done","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"88981ef4f7f76f1545c13ee2b28b8e06218df419","submitter":{"id":72557,"url":"http://patchwork.ozlabs.org/api/people/72557/?format=json","name":"Yixun Lan","email":"dlan@gentoo.org"},"delegate":{"id":114289,"url":"http://patchwork.ozlabs.org/api/users/114289/?format=json","username":"apritzel","first_name":"Andre","last_name":"Przywara","email":"andre.przywara@arm.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260421-02-spi-fifo-reset-v1-1-e2cdd4bd474d@gentoo.org/mbox/","series":[{"id":500725,"url":"http://patchwork.ozlabs.org/api/series/500725/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=500725","date":"2026-04-21T04:47:50","name":"spi: sunxi: wait for TX/RX fifo reset done","version":1,"mbox":"http://patchwork.ozlabs.org/series/500725/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225437/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225437/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Tue, 21 Apr 2026 06:48:11 +0200 (CEST)","from ofovo.local (unknown [116.232.124.22])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest\n SHA256)\n (No client certificate requested) (Authenticated sender: dlan)\n by smtp.gentoo.org (Postfix) with ESMTPSA id E8773342020;\n Tue, 21 Apr 2026 04:48:05 +0000 (UTC)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-1.9 required=5.0 tests=BAYES_00,\n RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,\n SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2","From":"Yixun Lan ","Date":"Tue, 21 Apr 2026 04:47:50 +0000","Subject":"[PATCH] spi: sunxi: wait for TX/RX fifo reset done","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260421-02-spi-fifo-reset-v1-1-e2cdd4bd474d@gentoo.org>","X-B4-Tracking":"v=1; b=H4sIAHUB52kC/x3MPQqAMAxA4auUzAba1B/wKuIgmmqWtjQignh3i\n +M3vPeAchFWGM0DhS9RSbHCNQbWY4k7o2zVQJZ6S2TREmoWDBISFlY+kTr2g/OuXX2A2uXCQe7\n /Oc3v+wH0nO7WYwAAAA==","X-Change-ID":"20260220-02-spi-fifo-reset-25e371314c3f","To":"u-boot@lists.denx.de","Cc":"linux-sunxi@lists.linux.dev, Andre Przywara ,\n Jagan Teki , Tom Rini ,\n Yixun Lan ","X-Mailer":"b4 0.14.3","X-Developer-Signature":"v=1; a=openpgp-sha256; l=1942; i=dlan@gentoo.org;\n h=from:subject:message-id; bh=HQ8gi3qkGDAytzDkMpwdgUvUWfOgiVivh5rYb7fjdrc=;\n b=owEB6QIW/ZANAwAKATGq6kdZTbvtAcsmYgBp5wGChkbAlN8OK0lV/mPLuSACAPd5BqFV5zmzk\n BGA+AoKQdaJAq8EAAEKAJkWIQS1urjJwxtxFWcCI9wxqupHWU277QUCaecBghsUgAAAAAAEAA5t\n YW51MiwyLjUrMS4xMSwyLDJfFIAAAAAALgAoaXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5\n maWZ0aGhvcnNlbWFuLm5ldEI1QkFCOEM5QzMxQjcxMTU2NzAyMjNEQzMxQUFFQTQ3NTk0REJCRU\n QACgkQMarqR1lNu+1x0Q/9HaxhtYzaHKO+PAlwGgyrBOrOKnyX2nQ3WozR0ltqr125Hau+SRAPq\n 9OCVmvKUpxbmx6IqB772GfabuVrr9F7GkRL1NHRCCB/gdj40B408YzYRc1vsK/4/xDlLEvEyZx4\n 9yEuMHvlrJCqACl9zfGVFzCHxurbmxWhIvo2O25DqPt+zON0SLB1QHnmZDLSyVn46EOKSAIxI6g\n ltMAucSg6UUKg9AIMbmjg/nJ9EG5kRbRKZcpWvGOvX8hvllsQIOu5W9CYGsheQbrmHdSgOH87Qc\n 1y1zp1MypRdmf14BKNYpyUxmpX0oDiw+uD2Y/W7UEiDtsSVueQsnofySASUwRn1ecFx+5Ex3QP/\n l8vjSDWpFxnUIVNKWFeA5tkmRRTdxQJyCXvRtbrJiYeaSPkWxnv9ICEHeoNTRt5DUYFRJydAfW5\n GlYQNOWt1NAQgu92ujg9Z772WNwq4x1ga6jSVwvD/TC+oa2yNk2MGPxCTfGNIhnFCzxHueIHUgh\n 4DVMBYgdZmH7OqasNZi+QrUV16BuqFua3xLGW2np9sZOFvaV2djNTXr70fgHoOogKp0S3Pa4Gx0\n 0j2gDBVX7c1GJeGh11e1D+t8b14nCxTcDiwzxpPeMRfPqD1A3PrxV45DoYixZgUxp7zD2hvzk+L\n piQzVEb2hRRBPeKLo4cu+1gkjeWoF0=","X-Developer-Key":"i=dlan@gentoo.org; a=openpgp;\n fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Once reset SPI TX or RX fifo, the underlying hardware need to take\nsome time to actually settle down, the two bits will automatically\nclear to 0, so use a poll mechanism to check status bits to make sure\nit's done correctly.\n\nSigned-off-by: Yixun Lan \n---\nOn Cubie A7A board which using A733 SoC, we encoutered a SPI nor flash\ntimeout issue, it turns out that the SPI fifo reset take a few time to\nsettle down, Add a loop to poll the status.\n\nThis was the error message shows on A7A board once this issue happened.\n\n=> sf probe\nERROR: sun4i_spi: Timeout transferring data\nFailed to initialize SPI flash at 0:0 (error -2)\n---\n drivers/spi/spi-sunxi.c | 9 ++++++---\n 1 file changed, 6 insertions(+), 3 deletions(-)\n\n\n---\nbase-commit: 88dc2788777babfd6322fa655df549a019aa1e69\nchange-id: 20260220-02-spi-fifo-reset-25e371314c3f\n\nBest regards,","diff":"diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c\nindex e00532a371b..cf41905c7b7 100644\n--- a/drivers/spi/spi-sunxi.c\n+++ b/drivers/spi/spi-sunxi.c\n@@ -347,7 +347,7 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,\n \tstruct sun4i_spi_priv *priv = dev_get_priv(bus);\n \tstruct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);\n \n-\tu32 len = bitlen / 8;\n+\tu32 rst, val, len = bitlen / 8;\n \tu8 nbytes;\n \tint ret;\n \n@@ -363,8 +363,11 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,\n \t\tsun4i_spi_set_cs(bus, slave_plat->cs[0], true);\n \n \t/* Reset FIFOs */\n-\tsetbits_le32(SPI_REG(priv, SPI_FCR), SPI_BIT(priv, SPI_FCR_RF_RST) |\n-\t\t SPI_BIT(priv, SPI_FCR_TF_RST));\n+\trst = SPI_BIT(priv, SPI_FCR_RF_RST) | SPI_BIT(priv, SPI_FCR_TF_RST);\n+\tsetbits_le32(SPI_REG(priv, SPI_FCR), rst);\n+\tret = readl_poll_timeout(SPI_REG(priv, SPI_FCR), val, !(rst & val), 20);\n+\tif (ret)\n+\t\treturn -EBUSY;\n \n \twhile (len) {\n \t\t/* Setup the transfer now... */\n","prefixes":[]}