{"id":2225425,"url":"http://patchwork.ozlabs.org/api/patches/2225425/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/aebobLlbeNmpoKQ8@cowardly-lion.the-meissners.org/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-04-21T03:01:00","name":"GCC 17.0 PowerPC patches V6 [PATCH 3/5]: Add xvrlw support.","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"7759eae614c2adc736a38752b472f61b5cbc5415","submitter":{"id":73991,"url":"http://patchwork.ozlabs.org/api/people/73991/?format=json","name":"Michael Meissner","email":"meissner@linux.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/aebobLlbeNmpoKQ8@cowardly-lion.the-meissners.org/mbox/","series":[{"id":500717,"url":"http://patchwork.ozlabs.org/api/series/500717/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=500717","date":"2026-04-21T03:01:00","name":"GCC 17.0 PowerPC patches V6 [PATCH 3/5]: Add xvrlw support.","version":1,"mbox":"http://patchwork.ozlabs.org/series/500717/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225425/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225425/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=UBMwQSyK;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","X-TM-AS-GCONF":"00","X-Proofpoint-ORIG-GUID":"Azh3roWsF91QdFLY7SAsA5jssWKImki-","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDIxMDAyNiBTYWx0ZWRfX8EM4rwbPMRLT\n +72nunIpd/4IHogXBhVik/wJFOu91GRJtnIfOkGIqJQ8cpGFihjMcZE9DqT2XFZ4VzhLDYe5GSl\n TYiN1NgOXNokdzkHV0R8VIyOIZwhTobJtxAbat27ZHCO6FA3Lt61D0B2+VYvrpp0tbNdpCKmfuR\n b2sFYc2zXUV6qVEAbvXMoZJs+53/d/6j/Xto6qt/FDLK5GpFxGpUg5VFz5yPncrDw3aW4eECM0R\n evuQOByfdWMcT17mGJjbv1GfC4Pm/gnF2s1RE1iW/Z9qofDmcfGeuqzvGuhkErkKPcQoirdJPz1\n 38mEMafUlTfwoNBXm3kfM3blRv9n0mPCj8Eg56Hap//7dQOHYSkZJkGgT7x8o2JmdeTim60RSrG\n WZYn612SawQiqRbJcrB2nn5rtenMnzUYqLJEbIrNvKBENbAEfXfGoQpZij4tx0ZQ1fEXg1OA+mQ\n Vk3I1nW/ZeJPefwqJ2Q==","X-Authority-Analysis":"v=2.4 cv=XLYAjwhE c=1 sm=1 tr=0 ts=69e6e872 cx=c_pps\n a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17\n a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=Y2IxJ9c9Rs8Kov3niI8_:22 a=mDV3o1hIAAAA:8\n a=VnNF1IyMAAAA:8 a=6MfUI2Q0x78_RvtHuRgA:9 a=CjuIK1q_8ugA:10","X-Proofpoint-GUID":"Azh3roWsF91QdFLY7SAsA5jssWKImki-","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-20_05,2026-04-20_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n clxscore=1015 bulkscore=0 impostorscore=0 spamscore=0 adultscore=0\n priorityscore=1501 phishscore=0 lowpriorityscore=0 malwarescore=0\n suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000\n definitions=main-2604210026","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"This patch adds support for a possible new variant of the vector rotate left\ninstruction that might be added to a future PowerPC. This variant (xvrlw) can\nuse any VSX register instead of requiring only Altivec registers.\n\nThis patch needs the -mcpu=future patch posted on April 8th, 2026:\n\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/712532.html\n\nI have built bootstrap little endian compilers on power10 systems, and\nbig endian compiler on power9 systems. There were no regression in the\ntests. Can I add the patches to the GCC trunk after the -mcpu=future\npatch is applied and GCC 17 has opened up?\n\ngcc/\n\n2026-04-20 Michael Meissner \n\n\t* config/rs6000/altivec.md (xvrlw): New insn.\n\t* config/rs6000/rs6000.h (TARGET_XVRLW): New macro.\n\n2026-04-20 Michael Meissner \n\ngcc/testsuite/\n\n\t* gcc.target/powerpc/vector-rotate-left.c: New test.\n---\n gcc/config/rs6000/altivec.md | 14 ++++++++\n gcc/config/rs6000/rs6000.h | 3 ++\n .../gcc.target/powerpc/vector-rotate-left.c | 34 +++++++++++++++++++\n 3 files changed, 51 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c","diff":"diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md\nindex 129f56245cd..51023c6bcfa 100644\n--- a/gcc/config/rs6000/altivec.md\n+++ b/gcc/config/rs6000/altivec.md\n@@ -1982,6 +1982,20 @@ (define_insn \"altivec_vpkuum_direct\"\n }\n [(set_attr \"type\" \"vecperm\")])\n \n+;; -mcpu=future adds a vector rotate left word variant. There is no vector\n+;; byte/half-word/double-word/quad-word rotate left. This insn occurs before\n+;; altivec_vrl and will match for -mcpu=future, while other cpus will\n+;; match the generic insn.\n+(define_insn \"*xvrlw\"\n+ [(set (match_operand:V4SI 0 \"register_operand\" \"=v,wa\")\n+\t(rotate:V4SI (match_operand:V4SI 1 \"register_operand\" \"v,wa\")\n+\t\t (match_operand:V4SI 2 \"register_operand\" \"v,wa\")))]\n+ \"TARGET_XVRLW\"\n+ \"@\n+ vrlw %0,%1,%2\n+ xvrlw %x0,%x1,%x2\"\n+ [(set_attr \"type\" \"vecsimple\")])\n+\n (define_insn \"altivec_vrl\"\n [(set (match_operand:VI2 0 \"register_operand\" \"=v\")\n (rotate:VI2 (match_operand:VI2 1 \"register_operand\" \"v\")\ndiff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h\nindex 23cef83ba17..f4c4060564e 100644\n--- a/gcc/config/rs6000/rs6000.h\n+++ b/gcc/config/rs6000/rs6000.h\n@@ -567,6 +567,9 @@ extern int rs6000_vector_align[];\n below. */\n #define RS6000_FN_TARGET_INFO_HTM 1\n \n+/* Whether we have XVRLW support. */\n+#define TARGET_XVRLW\t\t\tTARGET_FUTURE\n+\n /* Whether the various reciprocal divide/square root estimate instructions\n exist, and whether we should automatically generate code for the instruction\n by default. */\ndiff --git a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c\nnew file mode 100644\nindex 00000000000..f9e87ad4bfc\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c\n@@ -0,0 +1,34 @@\n+/* { dg-do compile } */\n+/* { dg-require-effective-target powerpc_future_ok } */\n+/* { dg-options \"-mdejagnu-cpu=future -O2\" } */\n+\n+/* Test whether the xvrl (vector word rotate left using VSX registers insead of\n+ Altivec registers is generated. */\n+\n+#include \n+\n+typedef vector unsigned int v4si_t;\n+\n+v4si_t\n+rotl_v4si_scalar (v4si_t x, unsigned long n)\n+{\n+ __asm__ (\" # %x0\" : \"+f\" (x));\n+ return (x << n) | (x >> (32 - n));\t/* xvrlw. */\n+}\n+\n+v4si_t\n+rotr_v4si_scalar (v4si_t x, unsigned long n)\n+{\n+ __asm__ (\" # %x0\" : \"+f\" (x));\n+ return (x >> n) | (x << (32 - n));\t/* xvrlw. */\n+}\n+\n+v4si_t\n+rotl_v4si_vector (v4si_t x, v4si_t y)\n+{\n+ __asm__ (\" # %x0\" : \"+f\" (x));\t/* xvrlw. */\n+ return vec_rl (x, y);\n+}\n+\n+/* { dg-final { scan-assembler-times {\\mxvrlw\\M} 3 } } */\n+/* { dg-final { scan-assembler-not {\\mvrlw\\M} } } */\n","prefixes":[]}