{"id":2225019,"url":"http://patchwork.ozlabs.org/api/patches/2225019/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260420170523.17908-2-junjie.cao@intel.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260420170523.17908-2-junjie.cao@intel.com>","list_archive_url":null,"date":"2026-04-20T17:05:23","name":"[2/2] tests/qtest: Add regression test for intel-iommu 8-byte MMIO access","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8f3805cfeaa274400224045c5a8ac5f5cfc72cb2","submitter":{"id":91537,"url":"http://patchwork.ozlabs.org/api/people/91537/?format=json","name":"Junjie Cao","email":"junjie.cao@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260420170523.17908-2-junjie.cao@intel.com/mbox/","series":[{"id":500573,"url":"http://patchwork.ozlabs.org/api/series/500573/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500573","date":"2026-04-20T17:05:22","name":"[1/2] intel_iommu: Replace assert(size == 4) with guest error in MMIO handlers","version":1,"mbox":"http://patchwork.ozlabs.org/series/500573/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225019/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225019/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=JItsd2ej;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fzffd5wZgz1yCv\n\tfor ; Mon, 20 Apr 2026 19:03:37 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wEkWp-0007sV-3p; Mon, 20 Apr 2026 05:02:51 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wEkWf-0007r9-EW\n for qemu-devel@nongnu.org; Mon, 20 Apr 2026 05:02:41 -0400","from mgamail.intel.com ([198.175.65.14])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wEkWd-0002EW-Uj\n for qemu-devel@nongnu.org; Mon, 20 Apr 2026 05:02:41 -0400","from orviesa002.jf.intel.com ([10.64.159.142])\n by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 20 Apr 2026 02:02:38 -0700","from junjie-optiplex-micro-plus-7010.bj.intel.com ([10.238.152.98])\n by orviesa002-auth.jf.intel.com with\n ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Apr 2026 02:02:34 -0700"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1776675760; x=1808211760;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=yxCLbt9+8utUs+QSmodG/CdePKqwm4ukEkB8XjX2Bxk=;\n b=JItsd2ejIRcLsiLsnXv94pC5fOGoyQ2INp36NTx5AqbwD+hLrmA4AWAg\n 4Moma0yljhi/eW8muIlpLX/j3QNKfGQRyE/LfksUZP3/NBcdGfT1mJGyF\n ahnukNLBegUw6Iu1tx2WbcmaqMeoCVYFYSa7FejJCHWtcLhfLbKBAPu5w\n b0IZhq9VvUuXjydufw9r4ZFqp2Wz95nCx+gzGcpWDx3WJjmn7fbl3bV7c\n t8kLygpS2I5C89P+ipkKK9GkVSZX6+0/258SXYQlVhC+sSrX9VMBwGWCH\n UvXi2DbvtYI60J+R+txtkTXGO1o021jb5t/dkHzSagtzszmeaha1itpCZ Q==;","X-CSE-ConnectionGUID":["zYGCnLl8RYKwnMxpN/z3Hw==","P4CPNNLQRbSR69NJKFo4cQ=="],"X-CSE-MsgGUID":["6tikYRxXQhmrDUS3McPIyw==","69PrzR9ARh+kdbkTcw3tTg=="],"X-IronPort-AV":["E=McAfee;i=\"6800,10657,11762\"; a=\"81457571\"","E=Sophos;i=\"6.23,189,1770624000\"; d=\"scan'208\";a=\"81457571\"","E=Sophos;i=\"6.23,189,1770624000\"; d=\"scan'208\";a=\"262049227\""],"X-ExtLoop1":"1","From":"Junjie Cao ","To":"qemu-devel@nongnu.org","Cc":"\"Michael S . Tsirkin\" , jasowang@redhat.com,\n yi.l.liu@intel.com,\n =?utf-8?q?Cl=C3=A9ment_Mathieu--Drif?= ,\n marcel.apfelbaum@gmail.com, pbonzini@redhat.com,\n richard.henderson@linaro.org, farosas@suse.de, lvivier@redhat.com,\n junjie.cao@intel.com","Subject":"[PATCH 2/2] tests/qtest: Add regression test for intel-iommu 8-byte\n MMIO access","Date":"Tue, 21 Apr 2026 01:05:23 +0800","Message-ID":"<20260420170523.17908-2-junjie.cao@intel.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260420170523.17908-1-junjie.cao@intel.com>","References":"<20260420170523.17908-1-junjie.cao@intel.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=198.175.65.14;\n envelope-from=junjie.cao@intel.com;\n helo=mgamail.intel.com","X-Spam_score_int":"-24","X-Spam_score":"-2.5","X-Spam_bar":"--","X-Spam_report":"(-2.5 / 5.0 requ) BAYES_00=-1.9, DATE_IN_FUTURE_06_12=1.947,\n DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1,\n DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Sweep every 4-byte-aligned offset in the VT-d MMIO register space\nwith 8-byte reads and writes to verify that no register handler\naborts on an oversized access.\n\nSigned-off-by: Junjie Cao \n---\n tests/qtest/intel-iommu-test.c | 36 ++++++++++++++++++++++++++++++++++\n 1 file changed, 36 insertions(+)","diff":"diff --git a/tests/qtest/intel-iommu-test.c b/tests/qtest/intel-iommu-test.c\nindex e5cc6acaf0..87a26b6910 100644\n--- a/tests/qtest/intel-iommu-test.c\n+++ b/tests/qtest/intel-iommu-test.c\n@@ -17,11 +17,45 @@\n #define ECAP_STAGE_1_FIXED1 (VTD_ECAP_QI | VTD_ECAP_IR | VTD_ECAP_IRO | \\\n VTD_ECAP_MHMV | VTD_ECAP_SMTS | VTD_ECAP_FSTS)\n \n+static inline uint32_t vtd_reg_readl(QTestState *s, uint64_t offset)\n+{\n+ return qtest_readl(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset);\n+}\n+\n static inline uint64_t vtd_reg_readq(QTestState *s, uint64_t offset)\n {\n return qtest_readq(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset);\n }\n \n+static inline void vtd_reg_writeq(QTestState *s, uint64_t offset,\n+ uint64_t value)\n+{\n+ qtest_writeq(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset, value);\n+}\n+\n+/*\n+ * Sweep every 4-byte-aligned offset in the VT-d register space with\n+ * an 8-byte read and write to verify that no 32-bit-only register\n+ * handler aborts on an oversized access.\n+ */\n+static void test_intel_iommu_8byte_access_sweep(void)\n+{\n+ QTestState *s;\n+ uint64_t off;\n+\n+ s = qtest_init(\"-M q35 -device intel-iommu\");\n+\n+ for (off = 0; off < DMAR_REG_SIZE; off += 4) {\n+ vtd_reg_readq(s, off);\n+ vtd_reg_writeq(s, off, 0);\n+ }\n+\n+ /* Liveness check: QEMU must still respond after the sweep */\n+ g_assert_cmpuint(vtd_reg_readl(s, DMAR_VER_REG), !=, 0);\n+\n+ qtest_quit(s);\n+}\n+\n static void test_intel_iommu_stage_1(void)\n {\n uint8_t init_csr[DMAR_REG_SIZE]; /* register values */\n@@ -58,6 +92,8 @@ static void test_intel_iommu_stage_1(void)\n int main(int argc, char **argv)\n {\n g_test_init(&argc, &argv, NULL);\n+ qtest_add_func(\"/q35/intel-iommu/8byte-access-sweep\",\n+ test_intel_iommu_8byte_access_sweep);\n qtest_add_func(\"/q35/intel-iommu/stage-1\", test_intel_iommu_stage_1);\n \n return g_test_run();\n","prefixes":["2/2"]}