{"id":2225018,"url":"http://patchwork.ozlabs.org/api/patches/2225018/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260420170523.17908-1-junjie.cao@intel.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260420170523.17908-1-junjie.cao@intel.com>","list_archive_url":null,"date":"2026-04-20T17:05:22","name":"[1/2] intel_iommu: Replace assert(size == 4) with guest error in MMIO handlers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8d3ed77a7c9b2c792f6108c8eff08c84fe4566cc","submitter":{"id":91537,"url":"http://patchwork.ozlabs.org/api/people/91537/?format=json","name":"Junjie Cao","email":"junjie.cao@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260420170523.17908-1-junjie.cao@intel.com/mbox/","series":[{"id":500573,"url":"http://patchwork.ozlabs.org/api/series/500573/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500573","date":"2026-04-20T17:05:22","name":"[1/2] intel_iommu: Replace assert(size == 4) with guest error in MMIO handlers","version":1,"mbox":"http://patchwork.ozlabs.org/series/500573/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2225018/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2225018/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=LkwaXP7r;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fzffW52SGz1yCv\n\tfor ; Mon, 20 Apr 2026 19:03:30 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wEkWk-0007rd-LZ; Mon, 20 Apr 2026 05:02:46 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wEkWe-0007r4-0G\n for qemu-devel@nongnu.org; Mon, 20 Apr 2026 05:02:41 -0400","from mgamail.intel.com ([198.175.65.14])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wEkWZ-0002DP-N0\n for qemu-devel@nongnu.org; Mon, 20 Apr 2026 05:02:38 -0400","from orviesa002.jf.intel.com ([10.64.159.142])\n by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 20 Apr 2026 02:02:31 -0700","from junjie-optiplex-micro-plus-7010.bj.intel.com ([10.238.152.98])\n by orviesa002-auth.jf.intel.com with\n ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Apr 2026 02:02:28 -0700"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1776675756; x=1808211756;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=0/HFh7EksONO9l1F5lm06dR81poht8axcQuF/OzYr88=;\n b=LkwaXP7rURWaoKbHvA6LKLZ9bO4z6v/xrb84k+XCXrnRVa9u4KJYsKnE\n 71KDhdc9mIi4rZQ7QFohl1TtRWPZApH4QIwrWMRyXcTUiDH2cr/iyH9QV\n gFvpJcOiGJztBoCGRiEjcui8BqvgB99knlbk9KBQ6L7yJp78gCayGd54J\n SlFQEbkK/VheAnS8+jhK+pAAI28znh/YQEI7rlaNzPRRYCj0jS1eZZVZT\n XxERgdBUFKrMpciG3GiZi1M4qKhIV0GBwzR83aZbiy2gROa2wBGCjSKy0\n XaQNN942e4XI2F2ADA4pSVEUvxY4l3p2RjVhTHxTSWbWdGnaHNIVJtCdV Q==;","X-CSE-ConnectionGUID":["9zco6mcaR6KrWuNYn685ug==","ZcQUMxpYS+uK7HbEclFNEw=="],"X-CSE-MsgGUID":["UIdU9xv2TreE1ZQfIxmNUQ==","KFqBIiwXRfydilCMWAd/Dg=="],"X-IronPort-AV":["E=McAfee;i=\"6800,10657,11762\"; a=\"81457562\"","E=Sophos;i=\"6.23,189,1770624000\"; d=\"scan'208\";a=\"81457562\"","E=Sophos;i=\"6.23,189,1770624000\"; d=\"scan'208\";a=\"262049195\""],"X-ExtLoop1":"1","From":"Junjie Cao ","To":"qemu-devel@nongnu.org","Cc":"\"Michael S . Tsirkin\" , jasowang@redhat.com,\n yi.l.liu@intel.com,\n =?utf-8?q?Cl=C3=A9ment_Mathieu--Drif?= ,\n marcel.apfelbaum@gmail.com, pbonzini@redhat.com,\n richard.henderson@linaro.org, farosas@suse.de, lvivier@redhat.com,\n junjie.cao@intel.com","Subject":"[PATCH 1/2] intel_iommu: Replace assert(size == 4) with guest error\n in MMIO handlers","Date":"Tue, 21 Apr 2026 01:05:22 +0800","Message-ID":"<20260420170523.17908-1-junjie.cao@intel.com>","X-Mailer":"git-send-email 2.43.0","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=198.175.65.14;\n envelope-from=junjie.cao@intel.com;\n helo=mgamail.intel.com","X-Spam_score_int":"-24","X-Spam_score":"-2.5","X-Spam_bar":"--","X-Spam_report":"(-2.5 / 5.0 requ) BAYES_00=-1.9, DATE_IN_FUTURE_06_12=1.947,\n DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1,\n DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"vtd_mem_read() and vtd_mem_write() use assert(size == 4) for\n32-bit-only VT-d registers. Since MemoryRegionOps .valid/.impl\naccepts sizes 4 through 8, an 8-byte guest access passes framework\nvalidation and reaches the handler, where the assertion aborts QEMU.\n\nNarrowing .impl.max_access_size to 4 is not viable because VT-d has\n64-bit registers (e.g. DMAR_CCMD_REG, DMAR_IQA_REG) that require\natomic 8-byte access to trigger command execution.\n\nReplace all 22 asserts in vtd_mem_write() and 3 in vtd_mem_read()\nwith a size check that logs via qemu_log_mask(LOG_GUEST_ERROR) and\nreturns without performing the register access. The asymmetry\n(22 vs 3) is because vtd_mem_read() handles most registers through\nits default branch, so only three explicit cases carried an assert.\n\nFound by fuzzing with QEMU's generic-fuzz framework; crashes\nreproduced at DMAR_FECTL_REG, DMAR_IECTL_REG, DMAR_IEADDR_REG\nand DMAR_PECTL_REG; all 25 sites share the same root cause.\n\nSigned-off-by: Junjie Cao \n---\n hw/i386/intel_iommu.c | 114 +++++++++++++++++++++++++++++++++---------\n 1 file changed, 89 insertions(+), 25 deletions(-)","diff":"diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex f395fa248c..1b91055eef 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -21,6 +21,7 @@\n \n #include \"qemu/osdep.h\"\n #include \"qemu/error-report.h\"\n+#include \"qemu/log.h\"\n #include \"qemu/main-loop.h\"\n #include \"qapi/error.h\"\n #include \"hw/core/sysbus.h\"\n@@ -3713,7 +3714,9 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)\n break;\n \n case DMAR_RTADDR_REG_HI:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n val = vtd_get_quad_raw(s, DMAR_RTADDR_REG) >> 32;\n break;\n \n@@ -3728,12 +3731,16 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)\n break;\n \n case DMAR_IQA_REG_HI:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n val = s->iq >> 32;\n break;\n \n case DMAR_PEUADDR_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n val = vtd_get_long_raw(s, DMAR_PEUADDR_REG);\n break;\n \n@@ -3746,6 +3753,12 @@ static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)\n }\n \n return val;\n+\n+err_width:\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"%s: invalid read size %u at offset 0x%\" PRIx64 \"\\n\",\n+ __func__, size, addr);\n+ return (uint64_t)-1;\n }\n \n static void vtd_mem_write(void *opaque, hwaddr addr,\n@@ -3779,7 +3792,9 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_CCMD_REG_HI:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n vtd_handle_ccmd_write(s);\n break;\n@@ -3795,13 +3810,17 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_IOTLB_REG_HI:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n vtd_handle_iotlb_write(s);\n break;\n \n case DMAR_PEUADDR_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n break;\n \n@@ -3815,27 +3834,35 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_IVA_REG_HI:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n break;\n \n /* Fault Status Register, 32-bit */\n case DMAR_FSTS_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n vtd_handle_fsts_write(s);\n break;\n \n /* Fault Event Control Register, 32-bit */\n case DMAR_FECTL_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n vtd_handle_fectl_write(s);\n break;\n \n /* Fault Event Data Register, 32-bit */\n case DMAR_FEDATA_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n break;\n \n@@ -3854,13 +3881,17 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n \n /* Fault Event Upper Address Register, 32-bit */\n case DMAR_FEUADDR_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n break;\n \n /* Protected Memory Enable Register, 32-bit */\n case DMAR_PMEN_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n break;\n \n@@ -3874,7 +3905,9 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_RTADDR_REG_HI:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n break;\n \n@@ -3889,7 +3922,9 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_IQT_REG_HI:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n /* 19:63 of IQT_REG is RsvdZ, do nothing here */\n break;\n@@ -3905,39 +3940,51 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_IQA_REG_HI:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n break;\n \n /* Invalidation Completion Status Register, 32-bit */\n case DMAR_ICS_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n vtd_handle_ics_write(s);\n break;\n \n /* Invalidation Event Control Register, 32-bit */\n case DMAR_IECTL_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n vtd_handle_iectl_write(s);\n break;\n \n /* Invalidation Event Data Register, 32-bit */\n case DMAR_IEDATA_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n break;\n \n /* Invalidation Event Address Register, 32-bit */\n case DMAR_IEADDR_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n break;\n \n /* Invalidation Event Upper Address Register, 32-bit */\n case DMAR_IEUADDR_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n break;\n \n@@ -3951,7 +3998,9 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_FRCD_REG_0_1:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n break;\n \n@@ -3966,7 +4015,9 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_FRCD_REG_0_3:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n /* May clear bit 127 (Fault), update PPF */\n vtd_update_fsts_ppf(s);\n@@ -3981,18 +4032,24 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n break;\n \n case DMAR_IRTA_REG_HI:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n break;\n \n case DMAR_PRS_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n vtd_handle_prs_write(s);\n break;\n \n case DMAR_PECTL_REG:\n- assert(size == 4);\n+ if (size != 4) {\n+ goto err_width;\n+ }\n vtd_set_long(s, addr, val);\n vtd_handle_pectl_write(s);\n break;\n@@ -4004,6 +4061,13 @@ static void vtd_mem_write(void *opaque, hwaddr addr,\n vtd_set_quad(s, addr, val);\n }\n }\n+\n+ return;\n+\n+err_width:\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"%s: invalid write size %u at offset 0x%\" PRIx64 \"\\n\",\n+ __func__, size, addr);\n }\n \n static void vtd_prepare_identity_entry(hwaddr addr, IOMMUAccessFlags perm,\n","prefixes":["1/2"]}