{"id":2224932,"url":"http://patchwork.ozlabs.org/api/patches/2224932/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260419173829.1074404-1-aswin.murugan@oss.qualcomm.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260419173829.1074404-1-aswin.murugan@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-19T17:38:29","name":"[v1] mach-snapdragon: Add KVM hypervisor support","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"ae96cb809a27e74dde7addfe87c640577befe93c","submitter":{"id":90811,"url":"http://patchwork.ozlabs.org/api/people/90811/?format=json","name":"Aswin Murugan","email":"aswin.murugan@oss.qualcomm.com"},"delegate":{"id":84350,"url":"http://patchwork.ozlabs.org/api/users/84350/?format=json","username":"narmstrong","first_name":"Neil","last_name":"Armstrong","email":"narmstrong@baylibre.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260419173829.1074404-1-aswin.murugan@oss.qualcomm.com/mbox/","series":[{"id":500521,"url":"http://patchwork.ozlabs.org/api/series/500521/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=500521","date":"2026-04-19T17:38:29","name":"[v1] mach-snapdragon: Add KVM hypervisor support","version":1,"mbox":"http://patchwork.ozlabs.org/series/500521/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224932/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224932/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=nqw7/hmn;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=UX3vA+9l;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"nqw7/hmn\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"UX3vA+9l\";\n\tdkim-atps=neutral","phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=aswin.murugan@oss.qualcomm.com"],"Received":["from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fzG7s5KXPz1yGt\n\tfor ; Mon, 20 Apr 2026 03:39:05 +1000 (AEST)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id F2D7183E81;\n\tSun, 19 Apr 2026 19:38:56 +0200 (CEST)","by phobos.denx.de (Postfix, from userid 109)\n id DEE8884181; Sun, 19 Apr 2026 19:38:55 +0200 (CEST)","from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id B0E7A839D9\n for ; Sun, 19 Apr 2026 19:38:52 +0200 (CEST)","from pps.filterd (m0279869.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63JGCU1n2107176\n for ; Sun, 19 Apr 2026 17:38:51 GMT","from mail-pf1-f197.google.com (mail-pf1-f197.google.com\n [209.85.210.197])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dm0y632vh-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for ; Sun, 19 Apr 2026 17:38:50 +0000 (GMT)","by mail-pf1-f197.google.com with SMTP id\n d2e1a72fcca58-82f7bec24fdso1390456b3a.2\n for ; Sun, 19 Apr 2026 10:38:50 -0700 (PDT)","from hu-aswinm-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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neil.armstrong@linaro.org,\n sumit.garg@kernel.org, aswin.murugan@oss.qualcomm.com,\n sughosh.ganu@arm.com, gchan9527@gmail.com, u-boot-qcom@groups.io,\n u-boot@lists.denx.de","Subject":"[PATCH v1] mach-snapdragon: Add KVM hypervisor support","Date":"Sun, 19 Apr 2026 23:08:29 +0530","Message-Id":"<20260419173829.1074404-1-aswin.murugan@oss.qualcomm.com>","X-Mailer":"git-send-email 2.34.1","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-ORIG-GUID":"AtxXdBqCXyXLy9p0SutJyOmb8votIZt4","X-Authority-Analysis":"v=2.4 cv=Fpo1OWrq c=1 sm=1 tr=0 ts=69e5132a cx=c_pps\n a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8\n a=v8_0fD8sVwdknlzlMUYA:9 a=2VI0MkxyNR6bbpdq8BZq:22","X-Proofpoint-GUID":"AtxXdBqCXyXLy9p0SutJyOmb8votIZt4","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDE5MDE4OCBTYWx0ZWRfXzSYoMWxffcpN\n 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engine=8.22.0-2604070000 definitions=main-2604190188","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Enable Linux KVM virtualization on Snapdragon SoCs.\n\nIntroduce CONFIG_QCOM_KVM_SUPPORT to select KVM or Gunyah\nhypervisor modes at build time.\n\nqcom-priv.h:\n - Add TrustZone SMC interface definitions and parameter IDs\n - Define hypervisor boot types (GUNYAH=0, KVM=1)\n - Add TCR_EL2 bit field definitions for memory config\n\nboard.c:\n - Add qcom_configure_kvm_hypervisor() with EL-aware logic\n - EL2: Perform direct SMC call for hypervisor setup\n - EL1: Save context, disable caches, run SMC, restore state,\n reconfigure TCR_EL2, re-enable caches\n - Add qcom_configure_gunyah_hypervisor() for standard flow\n - Add SCM service availability checks\n\nDefault mode remains Gunyah. Enable CONFIG_QCOM_KVM_SUPPORT to\nselect KVM for Linux.\n\nSigned-off-by: Aswin Murugan \n---\n arch/arm/mach-snapdragon/Kconfig | 7 ++\n arch/arm/mach-snapdragon/board.c | 154 +++++++++++++++++++++++++++\n arch/arm/mach-snapdragon/qcom-priv.h | 31 ++++++\n 3 files changed, 192 insertions(+)","diff":"diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig\nindex d3de8693b5a..2e5676945ca 100644\n--- a/arch/arm/mach-snapdragon/Kconfig\n+++ b/arch/arm/mach-snapdragon/Kconfig\n@@ -42,4 +42,11 @@ config SYS_CONFIG_NAME\n \t Based on this option include/configs/.h header\n \t will be used for board configuration.\n \n+config QCOM_KVM_SUPPORT\n+\tbool \"Enable KVM support for Qualcomm platforms\"\n+\tdepends on ARM64\n+\thelp\n+\t This configures the hypervisor interface during boot to support\n+\t KVM virtualization instead of the default Gunyah hypervisor.\n+\n endif\ndiff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c\nindex 5fb3240acc5..2926dd8ccc0 100644\n--- a/arch/arm/mach-snapdragon/board.c\n+++ b/arch/arm/mach-snapdragon/board.c\n@@ -510,6 +510,154 @@ void __weak qcom_late_init(void)\n {\n }\n \n+/**\n+ * qcom_configure_kvm_hypervisor() - Configure hypervisor for KVM guest mode\n+ *\n+ * Configures the hypervisor for KVM operation:\n+ * - EL2 path: Direct SMC call\n+ * - EL1 path: Save context, disable caches, SMC call, restore context\n+ *\n+ * Return: 0 on success, negative error code on failure\n+ */\n+static int qcom_configure_kvm_hypervisor(void)\n+{\n+\tstruct arm_smccc_res res;\n+\tu64 current_el;\n+\n+\tasm volatile(\"mrs %0, CurrentEL\" : \"=r\" (current_el));\n+\tcurrent_el = (current_el >> 2) & 0x3;\n+\n+\tlog_info(\"Configuring hypervisor for KVM (EL%llu)\\n\", current_el);\n+\n+\tarm_smccc_smc(TZ_INFO_IS_SVC_AVAILABLE_ID,\n+\t\t TZ_INFO_IS_SVC_AVAILABLE_ID_PARAM_ID,\n+\t\t TZ_CONFIGURE_MILESTONE_SERVICE_ID,\n+\t\t 0, 0, 0, 0, 0, &res);\n+\n+\tif (res.a0 != 0)\n+\t\tlog_debug(\"KVM milestone service not available (0x%lx)\\n\", res.a0);\n+\n+\tif (current_el == 2) {\n+\t\tlog_debug(\"At EL2\\n\");\n+\n+\t\tarm_smccc_smc(TZ_CONFIGURE_MILESTONE_SERVICE_ID,\n+\t\t\t TZ_CONFIGURE_MILESTONE_SERVICE_PARAM_ID,\n+\t\t\t 0, 0, QCOM_HYP_BOOT_TYPE_KVM,\n+\t\t\t 0, 0, 0, &res);\n+\n+\t\tif (res.a0 != 0) {\n+\t\t\tlog_err(\"Hypervisor configuration failed: 0x%lx\\n\", res.a0);\n+\t\t\treturn -EIO;\n+\t\t}\n+\n+\t\tlog_info(\"KVM hypervisor configured\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\tlog_debug(\"At EL1, saving register context\\n\");\n+\n+\tu64 ttbr0_el1, tcr_el1, tcr_el2, mair_el1;\n+\tu64 t0sz, phys_addr_size;\n+\n+\t/* Save EL1 system register context */\n+\tasm volatile(\"mrs %0, ttbr0_el1\" : \"=r\" (ttbr0_el1));\n+\tasm volatile(\"mrs %0, tcr_el1\" : \"=r\" (tcr_el1));\n+\tasm volatile(\"mrs %0, mair_el1\" : \"=r\" (mair_el1));\n+\n+\tt0sz = tcr_el1 & TCR_T0SZ_MASK;\n+\tphys_addr_size = tcr_el1 & TCR_PS_MASK;\n+\n+\tlog_debug(\"Saved context: TTBR0=0x%llx TCR=0x%llx MAIR=0x%llx\\n\",\n+\t\t ttbr0_el1, tcr_el1, mair_el1);\n+\n+\ticache_disable();\n+\tdcache_disable();\n+\n+\tarm_smccc_smc(TZ_CONFIGURE_MILESTONE_SERVICE_ID,\n+\t\t TZ_CONFIGURE_MILESTONE_SERVICE_PARAM_ID,\n+\t\t 0, 0, QCOM_HYP_BOOT_TYPE_KVM,\n+\t\t 0, 0, 0, &res);\n+\n+\tif (res.a0 != 0) {\n+\t\tlog_err(\"Hypervisor configuration failed: 0x%lx\\n\", res.a0);\n+\t\ticache_enable();\n+\t\tdcache_enable();\n+\t\treturn -EIO;\n+\t}\n+\n+\tasm volatile(\"mrs %0, CurrentEL\" : \"=r\" (current_el));\n+\tcurrent_el = (current_el >> 2) & 0x3;\n+\n+\tasm volatile(\"msr ttbr0_el1, %0\" : : \"r\" (ttbr0_el1));\n+\tasm volatile(\"isb\");\n+\n+\tif (current_el != 2) {\n+\t\tlog_debug(\"No EL2 transition, skipping TCR_EL2 config\\n\");\n+\t\ticache_enable();\n+\t\tdcache_enable();\n+\t\tlog_warning(\"KVM hypervisor configuration failed\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\t/* Read current TCR_EL2 and reconfigure it */\n+\tasm volatile(\"mrs %0, tcr_el2\" : \"=r\" (tcr_el2));\n+\n+\ttcr_el2 &= ~(TCR_T0SZ_MASK | (0x7UL << 16));\n+\ttcr_el2 |= t0sz | (phys_addr_size >> TCR_PS_SHIFT);\n+\n+\ttcr_el2 &= ~TCR_SH_ORGN_IRGN_MASK;\n+\ttcr_el2 |= TCR_SH_INNER_SHAREABLE |\n+\t\t TCR_ORGN_WRITE_BACK_ALLOC |\n+\t\t TCR_IRGN_WRITE_BACK_ALLOC;\n+\n+\tasm volatile(\"msr tcr_el2, %0\" : : \"r\" (tcr_el2));\n+\tasm volatile(\"msr mair_el1, %0\" : : \"r\" (mair_el1));\n+\tasm volatile(\"isb\");\n+\n+\ticache_enable();\n+\tdcache_enable();\n+\n+\tlog_info(\"KVM hypervisor configured\\n\");\n+\treturn 0;\n+}\n+\n+/**\n+ * qcom_configure_gunyah_hypervisor() - Configure hypervisor for Gunyah mode\n+ *\n+ * Configures the hypervisor for standard Gunyah operation.\n+ *\n+ * Return: 0 on success, negative error code on failure\n+ */\n+static int qcom_configure_gunyah_hypervisor(void)\n+{\n+\tstruct arm_smccc_res res;\n+\n+\tlog_info(\"Configuring hypervisor for Gunyah mode\\n\");\n+\n+\tarm_smccc_smc(TZ_INFO_IS_SVC_AVAILABLE_ID,\n+\t\t TZ_INFO_IS_SVC_AVAILABLE_ID_PARAM_ID,\n+\t\t TZ_CONFIGURE_MILESTONE_SERVICE_ID,\n+\t\t 0, 0, 0, 0, 0, &res);\n+\n+\tif (res.a0 != 0) {\n+\t\tlog_debug(\"Hypervisor milestone service not available (0x%lx)\\n\", res.a0);\n+\t\treturn 0;\n+\t}\n+\n+\tarm_smccc_smc(TZ_CONFIGURE_MILESTONE_SERVICE_ID,\n+\t\t TZ_CONFIGURE_MILESTONE_SERVICE_PARAM_ID,\n+\t\t 0, 0, QCOM_HYP_BOOT_TYPE_GUNYAH,\n+\t\t 0, 0, 0, &res);\n+\n+\tif (res.a0 != 0) {\n+\t\tlog_err(\"Hypervisor configuration failed: 0x%lx\\n\", res.a0);\n+\t\treturn -EIO;\n+\t}\n+\n+\tlog_info(\"Gunyah hypervisor configured\\n\");\n+\treturn 0;\n+}\n+\n #define KERNEL_COMP_SIZE\tSZ_64M\narch/arm/mach-snapdragon/Kconfig #ifdef CONFIG_FASTBOOT_BUF_SIZE\n #define FASTBOOT_BUF_SIZE CONFIG_FASTBOOT_BUF_SIZE\n@@ -570,6 +718,12 @@ int board_late_init(void)\n \tqcom_late_init();\n \n \tqcom_show_boot_source();\n+\n+\tif (IS_ENABLED(CONFIG_QCOM_KVM_SUPPORT))\n+\t\tqcom_configure_kvm_hypervisor();\n+\telse\n+\t\tqcom_configure_gunyah_hypervisor();\n+\n \t/* Configure the dfu_string for capsule updates */\n \tqcom_configure_capsule_updates();\n \ndiff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h\nindex b8bf574e8bb..a5d9dec6aa7 100644\n--- a/arch/arm/mach-snapdragon/qcom-priv.h\n+++ b/arch/arm/mach-snapdragon/qcom-priv.h\n@@ -17,6 +17,37 @@ enum qcom_boot_source {\n \n extern enum qcom_boot_source qcom_boot_source;\n \n+/* TrustZone SMC definitions */\n+#define TZ_SYSCALL_CREATE_SMC_ID(o, s, f) \\\n+\t((u32)((((o) & 0x3f) << 24) | (((s) & 0xff) << 8) | ((f) & 0xff)))\n+\n+#define TZ_OWNER_SIP\t\t\t\t2\n+#define TZ_SVC_BOOT\t\t\t\t1\n+#define TZ_SVC_INFO\t\t\t\t6\n+#define TZ_BOOT_CMD_KVM_MILESTONE\t\t0x21\n+#define TZ_INFO_IS_SVC_AVAILABLE_CMD\t\t0x01\n+\n+#define TZ_CONFIGURE_MILESTONE_SERVICE_ID \\\n+\tTZ_SYSCALL_CREATE_SMC_ID(TZ_OWNER_SIP, TZ_SVC_BOOT, TZ_BOOT_CMD_KVM_MILESTONE)\n+#define TZ_CONFIGURE_MILESTONE_SERVICE_PARAM_ID\t\t0x23\n+\n+#define TZ_INFO_IS_SVC_AVAILABLE_ID \\\n+\tTZ_SYSCALL_CREATE_SMC_ID(TZ_OWNER_SIP, TZ_SVC_INFO, TZ_INFO_IS_SVC_AVAILABLE_CMD)\n+#define TZ_INFO_IS_SVC_AVAILABLE_ID_PARAM_ID\t\t0x1\n+\n+/* Hypervisor boot types */\n+#define QCOM_HYP_BOOT_TYPE_GUNYAH\t\t0\n+#define QCOM_HYP_BOOT_TYPE_KVM\t\t\t1\n+\n+/* TCR_EL2 bit field definitions */\n+#define TCR_T0SZ_MASK\t\t\t\t0x1FUL\n+#define TCR_PS_MASK\t\t\t\t(0x7UL << 32)\n+#define TCR_PS_SHIFT\t\t\t\t16\n+#define TCR_SH_ORGN_IRGN_MASK\t\t\t0x3F00UL\n+#define TCR_SH_INNER_SHAREABLE\t\t\t(3UL << 12)\n+#define TCR_ORGN_WRITE_BACK_ALLOC\t\tBIT(10)\n+#define TCR_IRGN_WRITE_BACK_ALLOC\t\tBIT(8)\n+\n #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)\n void qcom_configure_capsule_updates(void);\n #else\n","prefixes":["v1"]}