{"id":2224849,"url":"http://patchwork.ozlabs.org/api/patches/2224849/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260418223320.51330-36-mohamed@unpredictable.fr/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260418223320.51330-36-mohamed@unpredictable.fr>","list_archive_url":null,"date":"2026-04-18T22:33:17","name":"[35/38] target/i386: emulate, hvf: rdmsr/wrmsr GPF handling","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6a49a4c2e13f9560e327963a5531411212882122","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/people/91318/?format=json","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260418223320.51330-36-mohamed@unpredictable.fr/mbox/","series":[{"id":500475,"url":"http://patchwork.ozlabs.org/api/series/500475/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500475","date":"2026-04-18T22:32:54","name":"WHPX x86 updates for QEMU 11.1","version":1,"mbox":"http://patchwork.ozlabs.org/series/500475/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224849/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224849/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=a4z+863N;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fymq53Jwxz1yGt\n\tfor ; Sun, 19 Apr 2026 08:37:53 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wEEFM-0008CC-TK; Sat, 18 Apr 2026 18:34:40 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wEEFL-00086A-Go\n for qemu-devel@nongnu.org; Sat, 18 Apr 2026 18:34:39 -0400","from p-east2-cluster1-host12-snip4-9.eps.apple.com ([57.103.76.62]\n helo=outbound.st.icloud.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wEEFJ-0005FL-Ps\n for qemu-devel@nongnu.org; Sat, 18 Apr 2026 18:34:39 -0400","from outbound.st.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-1 (Postfix) with ESMTPS id\n 27F4418000FC; Sat, 18 Apr 2026 22:34:32 +0000 (UTC)","from localhost.localdomain (unknown [17.42.251.67])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-1 (Postfix) with ESMTPSA id\n 56EA418000C4; Sat, 18 Apr 2026 22:34:27 +0000 (UTC)"],"Dkim-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1776551677; x=1779143677;\n bh=IdjugA9xaHsg2nQQQ2yDxOQbJO+pfnS1V2J1m3byuQQ=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme;\n b=a4z+863NLCY/pk5Ci0Ocdvvsm9s/V/H7GtFjDWUWtBlHkLwOf+3YhEoL2yb+mltaNtkc6ma1pmy7DLiMZpLmF0/lGwqZWtyVsZ/0G1mn74oykbB2vrtcfmri9mGlGjzRNeOSeA7RBqJZjLVV+es8cii7MZfqCy42lkEMy+ZgFrUtgJvb9EhCWF2w22qjnT/ObV3cTb/lrRcT09KsvX2EaIZA4CXoWzIG8z78rLWgzSOsDcEM+iAhAyfI7efKc1V2LrmJdDw34fpJokKgTthVnyeMAslffwrBRJmLny/SwmC1cYMBrIoUBOUBy7Zi9VWdz/M2INuIevO6C9TARvS3tw==","mail-alias-created-date":"1752046281608","From":"Mohamed Mediouni ","To":"qemu-devel@nongnu.org","Cc":"Mohamed Mediouni ,\n \"Michael S. Tsirkin\" , Paolo Bonzini ,\n Zhao Liu , Pedro Barbuda ,\n Roman Bolshakov , qemu-arm@nongnu.org,\n Pierrick Bouvier ,\n Peter Maydell , Wei Liu ,\n Phil Dennis-Jordan ","Subject":"[PATCH 35/38] target/i386: emulate, hvf: rdmsr/wrmsr GPF handling","Date":"Sun, 19 Apr 2026 00:33:17 +0200","Message-ID":"<20260418223320.51330-36-mohamed@unpredictable.fr>","X-Mailer":"git-send-email 2.50.1","In-Reply-To":"<20260418223320.51330-1-mohamed@unpredictable.fr>","References":"<20260418223320.51330-1-mohamed@unpredictable.fr>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-ORIG-GUID":"7Qp_TFdQSh-AecfZVKQKi9wOybeSg3Bf","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDE4MDIyOSBTYWx0ZWRfXylI5f6QgvWm3\n hccw+XSHHF6qrZaaXPg7YqUNP67fYJFoKrw+8y/Lf4nzGpZmMQwaa+eIEN+KMu9OYosKx1WzzaX\n 49Nknp28P2p/7qeuYbSvN/dBP2vxQK22WNmKDN9jRTkpWP3eeCUPBA0uDwG9sanHIYhLBHUDqZ/\n 9PZ2seme0bdTeXLbr83dHPJhea1HF44s2omv9iV6CUeIhEvZ74cjt7tkXW5+KGOiZ1P2Hn3+eyN\n hby9ljBhbx80O7ByHUq1QwPJE1BOOhzhUFYl8aGW4mydxKrnt9sVv4wqJERnYD9eZTgVeJDSDMl\n GFvWc+Wg9uzWzsJZaJhWct65+34nuARwUoSADN7LBwGXpYTltgvxUuL4+p4ye0=","X-Proofpoint-GUID":"7Qp_TFdQSh-AecfZVKQKi9wOybeSg3Bf","X-Authority-Info-Out":"v=2.4 cv=W9M1lBWk c=1 sm=1 tr=0 ts=69e406fb\n cx=c_apl:c_pps:t_out a=YrL12D//S6tul8v/L+6tKg==:117\n a=YrL12D//S6tul8v/L+6tKg==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=183X19KWV2qSZiVN73EA:9","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-18_06,2026-04-17_04,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=notspam policy=default score=0 bulkscore=0\n spamscore=0 mlxlogscore=697 lowpriorityscore=0 clxscore=1030 adultscore=0\n malwarescore=0 suspectscore=0 phishscore=0 mlxscore=0 classifier=spam\n authscore=0 adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000\n definitions=main-2604180229","Received-SPF":"pass client-ip=57.103.76.62;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"In that case, the instruction pointer mustn't be incremented.\n\nSigned-off-by: Mohamed Mediouni \n---\n target/i386/emulate/x86_emu.c | 10 ++++++----\n target/i386/emulate/x86_emu.h | 4 ++--\n target/i386/hvf/hvf.c | 9 +++++++--\n 3 files changed, 15 insertions(+), 8 deletions(-)","diff":"diff --git a/target/i386/emulate/x86_emu.c b/target/i386/emulate/x86_emu.c\nindex c2da1a133f..c6ea854290 100644\n--- a/target/i386/emulate/x86_emu.c\n+++ b/target/i386/emulate/x86_emu.c\n@@ -792,15 +792,17 @@ void x86_emul_raise_exception(CPUX86State *env, int exception_index, int error_c\n \n static bool exec_rdmsr(CPUX86State *env, struct x86_decode *decode)\n {\n- emul_ops->simulate_rdmsr(env_cpu(env));\n- env->eip += decode->len;\n+ if (!emul_ops->simulate_rdmsr(env_cpu(env))) {\n+ env->eip += decode->len;\n+ }\n return 0;\n }\n \n static bool exec_wrmsr(CPUX86State *env, struct x86_decode *decode)\n {\n- emul_ops->simulate_wrmsr(env_cpu(env));\n- env->eip += decode->len;\n+ if (!emul_ops->simulate_wrmsr(env_cpu(env))) {\n+ env->eip += decode->len;\n+ }\n return 0;\n }\n \ndiff --git a/target/i386/emulate/x86_emu.h b/target/i386/emulate/x86_emu.h\nindex a8d4c93098..b985240b90 100644\n--- a/target/i386/emulate/x86_emu.h\n+++ b/target/i386/emulate/x86_emu.h\n@@ -31,8 +31,8 @@ struct x86_emul_ops {\n target_ulong (*read_cr) (CPUState *cpu, int cr);\n void (*handle_io)(CPUState *cpu, uint16_t port, void *data, int direction,\n int size, int count);\n- void (*simulate_rdmsr)(CPUState *cs);\n- void (*simulate_wrmsr)(CPUState *cs);\n+ bool (*simulate_rdmsr)(CPUState *cs);\n+ bool (*simulate_wrmsr)(CPUState *cs);\n bool (*is_protected_mode)(CPUState *cpu);\n bool (*is_long_mode)(CPUState *cpu);\n bool (*is_user_mode)(CPUState *cpu);\ndiff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c\nindex c0d028b147..dfe7500010 100644\n--- a/target/i386/hvf/hvf.c\n+++ b/target/i386/hvf/hvf.c\n@@ -536,7 +536,7 @@ void hvf_store_regs(CPUState *cs)\n macvm_set_rip(cs, env->eip);\n }\n \n-void hvf_simulate_rdmsr(CPUState *cs)\n+bool hvf_simulate_rdmsr(CPUState *cs)\n {\n X86CPU *cpu = X86_CPU(cs);\n CPUX86State *env = &cpu->env;\n@@ -557,6 +557,7 @@ void hvf_simulate_rdmsr(CPUState *cs)\n ret = apic_msr_read(cpu->apic_state, index, &val);\n if (ret < 0) {\n x86_emul_raise_exception(env, EXCP0D_GPF, 0);\n+ return 1;\n }\n \n break;\n@@ -639,9 +640,10 @@ void hvf_simulate_rdmsr(CPUState *cs)\n \n RAX(env) = (uint32_t)val;\n RDX(env) = (uint32_t)(val >> 32);\n+ return 0;\n }\n \n-void hvf_simulate_wrmsr(CPUState *cs)\n+bool hvf_simulate_wrmsr(CPUState *cs)\n {\n X86CPU *cpu = X86_CPU(cs);\n CPUX86State *env = &cpu->env;\n@@ -657,6 +659,7 @@ void hvf_simulate_wrmsr(CPUState *cs)\n r = cpu_set_apic_base(cpu->apic_state, data);\n if (r < 0) {\n x86_emul_raise_exception(env, EXCP0D_GPF, 0);\n+ return 1;\n }\n \n break;\n@@ -668,6 +671,7 @@ void hvf_simulate_wrmsr(CPUState *cs)\n ret = apic_msr_write(cpu->apic_state, index, data);\n if (ret < 0) {\n x86_emul_raise_exception(env, EXCP0D_GPF, 0);\n+ return 1;\n }\n \n break;\n@@ -746,6 +750,7 @@ void hvf_simulate_wrmsr(CPUState *cs)\n g_hypervisor_iface->wrmsr_handler(cs, msr, data);\n \n printf(\"write msr %llx\\n\", RCX(cs));*/\n+ return 0;\n }\n \n static int hvf_handle_vmexit(CPUState *cpu)\n","prefixes":["35/38"]}