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In single/dual phase mode, registers of both regulators,\nmust be identically set. So configure mode and value for both BUCKs.\n\nCONF registers are not touched, leave them as default OTP settings.\n\nPFUZE100/200 SW3A/B, could work in single/dual phase mode, so introduce\na new macro by adding a pointer to the SW3B descriptor.\n\nSigned-off-by: Peng Fan \n---\n drivers/power/regulator/pfuze100.c | 49 ++++++++++++++++++++++++++++++++++----\n 1 file changed, 45 insertions(+), 4 deletions(-)","diff":"diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c\nindex ed69e6e14c3..77c82a00b65 100644\n--- a/drivers/power/regulator/pfuze100.c\n+++ b/drivers/power/regulator/pfuze100.c\n@@ -33,6 +33,8 @@ struct pfuze100_high_volt_desc {\n * @voltage: Current voltage for REGULATOR_TYPE_FIXED type regulator.\n * @high_volt_mask: Low or High Output voltage mode mask\n * @high_volt_desc: High Output voltage description\n+ * @b: Some regulators could work together to provide one output when working\n+ * in single phase or dual phase mode.\n */\n struct pfuze100_regulator_desc {\n \tchar *name;\n@@ -47,6 +49,7 @@ struct pfuze100_regulator_desc {\n \tunsigned int voltage;\n \tunsigned int high_volt_mask;\n \tstruct pfuze100_high_volt_desc *high_volt_desc;\n+\tstruct pfuze100_regulator_desc *b;\n };\n \n /**\n@@ -79,6 +82,21 @@ struct pfuze100_regulator_plat {\n \t\t.high_volt_mask\t=\t(mask),\t\t\t\t\\\n \t}\n \n+#define PFUZE100_SWAB_REG(_name, base, step, min, volt_desc, mask, desc)\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.name\t\t=\t#_name,\t\t\t\t\\\n+\t\t.type\t\t=\tREGULATOR_TYPE_BUCK,\t\t\\\n+\t\t.uV_step\t=\t(step),\t\t\t\t\\\n+\t\t.min_uV\t\t=\t(min),\t\t\t\t\\\n+\t\t.vsel_reg\t=\t(base) + PFUZE100_VOL_OFFSET,\t\\\n+\t\t.vsel_mask\t=\t0x3F,\t\t\t\t\\\n+\t\t.stby_reg\t=\t(base) + PFUZE100_STBY_OFFSET,\t\\\n+\t\t.stby_mask\t=\t0x3F,\t\t\t\t\\\n+\t\t.high_volt_desc\t=\t(volt_desc),\t\t\t\\\n+\t\t.high_volt_mask\t=\t(mask),\t\t\t\t\\\n+\t\t.b\t\t=\t(desc),\t\t\t\t\\\n+\t}\n+\n #define PFUZE100_SWB_REG(_name, base, mask, step, voltages)\t\t\\\n \t{\t\t\t\t\t\t\t\t\\\n \t\t.name\t\t=\t#_name,\t\t\t\t\\\n@@ -184,6 +202,8 @@ static struct pfuze100_regulator_desc pfuze100_regulators[] = {\n \tPFUZE100_SW_REG(sw1c, PFUZE100_SW1CVOL, 25000, 300000, NULL, 0),\n \tPFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000, 400000, &high_desc, BIT(6)),\n \tPFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000, 400000, &high_desc, BIT(6)),\n+\tPFUZE100_SWAB_REG(sw3ab, PFUZE100_SW3AVOL, 25000, 400000, &high_desc, BIT(6),\n+\t\t\t &pfuze100_regulators[5]),\n \tPFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000, 400000, &high_desc, BIT(6)),\n \tPFUZE100_SW_REG(sw4, PFUZE100_SW4VOL, 25000, 400000, &high_desc, BIT(6)),\n \tPFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst),\n@@ -202,6 +222,8 @@ static struct pfuze100_regulator_desc pfuze200_regulators[] = {\n \tPFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000, 300000, NULL, 0),\n \tPFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000, 400000, &high_desc, BIT(6)),\n \tPFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000, 400000, &high_desc, BIT(6)),\n+\tPFUZE100_SWAB_REG(sw3ab, PFUZE100_SW3AVOL, 25000, 400000, &high_desc, BIT(6),\n+\t\t\t &pfuze200_regulators[4]),\n \tPFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000, 400000, &high_desc, BIT(6)),\n \tPFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst),\n \tPFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),\n@@ -380,6 +402,16 @@ static int pfuze100_regulator_mode(struct udevice *dev, int op, int *opmode)\n \t\t\t\t desc->vsel_reg + PFUZE100_MODE_OFFSET,\n \t\t\t\t SW_MODE_MASK,\n \t\t\t\t *opmode << SW_MODE_SHIFT);\n+\t\tif (val)\n+\t\t\treturn val;\n+\n+\t\tif (desc->b) {\n+\t\t\tdesc = desc->b;\n+\t\t\tval = pmic_clrsetbits(dev->parent,\n+\t\t\t\t\t desc->vsel_reg + PFUZE100_MODE_OFFSET,\n+\t\t\t\t\t SW_MODE_MASK,\n+\t\t\t\t\t *opmode << SW_MODE_SHIFT);\n+\t\t}\n \n \t} else if (desc->type == REGULATOR_TYPE_LDO) {\n \t\tval = pmic_clrsetbits(dev->parent, desc->vsel_reg,\n@@ -458,7 +490,7 @@ static int pfuze100_regulator_enable(struct udevice *dev, int op, bool *enable)\n \n static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV)\n {\n-\tint i;\n+\tint i, ret;\n \tint val, min_uV, uV_step;\n \tstruct pfuze100_regulator_plat *plat = dev_get_plat(dev);\n \tstruct pfuze100_regulator_desc *desc = plat->desc;\n@@ -526,9 +558,18 @@ static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV)\n \t\t\tuV_step = desc->uV_step;\n \t\t}\n \n-\t\treturn pmic_clrsetbits(dev->parent, desc->vsel_reg,\n-\t\t\t\t desc->vsel_mask,\n-\t\t\t\t (*uV - min_uV) / uV_step);\n+\t\tret = pmic_clrsetbits(dev->parent, desc->vsel_reg,\n+\t\t\t\t desc->vsel_mask, (*uV - min_uV) / uV_step);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tif (desc->b) {\n+\t\t\tdesc = desc->b;\n+\t\t\tret = pmic_clrsetbits(dev->parent, desc->vsel_reg,\n+\t\t\t\t\t desc->vsel_mask, (*uV - min_uV) / uV_step);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t}\n \t}\n \n \treturn 0;\n","prefixes":["3/4"]}