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charset=\"iso-8859-1\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","X-OriginatorOrg":"htecgroup.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"PA3PR09MB8140.eurprd09.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 64b1228e-ca28-4772-9e1b-08de9c7c7290","X-MS-Exchange-CrossTenant-originalarrivaltime":"17 Apr 2026 12:25:44.4667 (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"9f85665b-7efd-4776-9dfe-b6bfda2565ee","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n LQfaAYkxPlAQeG8W1/85ks/mjYJmIo+/UsHzYs5EvK6QREh2vHxFJ7VIpgBGmn1PHkypcT1UEVE22Pk+iF/zPYCMKszrVEAcSikp3zRq+XM=","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DB9PR09MB6861","X-Mailman-Approved-At":"Fri, 17 Apr 2026 14:43:59 +0200","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"From: Chao-ying Fu \n\nAvoid writing to PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers for\nbus 0, device 0 (the root bridge) in the Xilinx PCIe driver.\n\nOn platforms such as the MIPS Boston board, writing to these fields\nresults in incorrect values (e.g. base = 0x0, limit = 0x1600), which\ncauses Linux to fail PCIe memory space assignment.\n\nAs a result, Linux can boot successfully and probe the PCIe bus and\nall connected devices on platforms like the MIPS Boston board.\n\nSigned-off-by: Chao-ying Fu \nSigned-off-by: Uros Stajic \n---\n drivers/pci/pcie_xilinx.c | 9 +++++++++\n 1 file changed, 9 insertions(+)","diff":"diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c\nindex 63058e8e7c5..4ef20474a0b 100644\n--- a/drivers/pci/pcie_xilinx.c\n+++ b/drivers/pci/pcie_xilinx.c\n@@ -132,6 +132,15 @@ static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf,\n \t\t\t\t uint offset, ulong value,\n \t\t\t\t enum pci_size_t size)\n {\n+\tif (bdf == PCI_BDF(bus->seq_, 0, 0)) {\n+\t\tswitch (offset) {\n+\t\tcase PCI_MEMORY_BASE:\n+\t\tcase PCI_MEMORY_LIMIT:\n+\t\t\t/* Writing the memory base or limit causes problems */\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n \treturn pci_generic_mmap_write_config(bus, pcie_xilinx_config_address,\n \t\t\t\t\t bdf, offset, value, size);\n }\n","prefixes":["v7","4/7"]}