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charset=\"utf-8\"","Content-ID":"<2FD6A6C4433CFA4DA1B1D8318FBD6CBD@eurprd09.prod.outlook.com>","Content-Transfer-Encoding":"base64","MIME-Version":"1.0","X-OriginatorOrg":"htecgroup.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-AuthSource":"PA3PR09MB8140.eurprd09.prod.outlook.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n c9413936-abb3-47d1-8511-08de9c7c38f8","X-MS-Exchange-CrossTenant-originalarrivaltime":"17 Apr 2026 12:24:07.8300 (UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"9f85665b-7efd-4776-9dfe-b6bfda2565ee","X-MS-Exchange-CrossTenant-mailboxtype":"HOSTED","X-MS-Exchange-CrossTenant-userprincipalname":"\n rAuPZdtLNk+OOu8T6mN4WFF7gOFh6Jt/vlmMuuLBJkLDxAgloG/TF4G1QILnYJ4LpTRQYWkAWnEHjg/T3Egh7cXEzZXJsn1yWhKy1zjF05s=","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"AS5PR09MB8577","X-Mailman-Approved-At":"Fri, 17 Apr 2026 14:43:59 +0200","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"From: Chao-ying Fu \n\nAdd initial platform support for the P8700-F, a high-performance\nmulti-core RV64GC SoC with optional multi-cluster configuration and\nhardware multithreading.\n\nThis patch introduces the initial platform code necessary to support\nthe P8700 CPU in U-Boot.\n\nReviewed-by: Leo Yu-Chi Liang \nSigned-off-by: Chao-ying Fu \nSigned-off-by: Uros Stajic \n---\n arch/riscv/Kconfig | 1 +\n arch/riscv/cpu/p8700/Kconfig | 21 +++++\n arch/riscv/cpu/p8700/Makefile | 8 ++\n arch/riscv/cpu/p8700/cache.c | 93 +++++++++++++++++++\n arch/riscv/cpu/p8700/cpu.c | 105 ++++++++++++++++++++++\n arch/riscv/cpu/p8700/dram.c | 37 ++++++++\n arch/riscv/cpu/p8700/p8700.c | 12 +++\n arch/riscv/include/asm/arch-p8700/p8700.h | 101 +++++++++++++++++++++\n 8 files changed, 378 insertions(+)\n create mode 100644 arch/riscv/cpu/p8700/Kconfig\n create mode 100644 arch/riscv/cpu/p8700/Makefile\n create mode 100644 arch/riscv/cpu/p8700/cache.c\n create mode 100644 arch/riscv/cpu/p8700/cpu.c\n create mode 100644 arch/riscv/cpu/p8700/dram.c\n create mode 100644 arch/riscv/cpu/p8700/p8700.c\n create mode 100644 arch/riscv/include/asm/arch-p8700/p8700.h","diff":"diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig\r\nindex ad7589123c6..d3380c3ac3f 100644\r\n--- a/arch/riscv/Kconfig\r\n+++ b/arch/riscv/Kconfig\r\n@@ -136,6 +136,7 @@ source \"arch/riscv/cpu/jh7110/Kconfig\"\r\n source \"arch/riscv/cpu/k1/Kconfig\"\r\n source \"arch/riscv/cpu/k230/Kconfig\"\r\n source \"arch/riscv/cpu/th1520/Kconfig\"\r\n+source \"arch/riscv/cpu/p8700/Kconfig\"\r\n \r\n # architecture-specific options below\r\n \r\ndiff --git a/arch/riscv/cpu/p8700/Kconfig b/arch/riscv/cpu/p8700/Kconfig\r\nnew file mode 100644\r\nindex 00000000000..bcd4c63fec7\r\n--- /dev/null\r\n+++ b/arch/riscv/cpu/p8700/Kconfig\r\n@@ -0,0 +1,21 @@\r\n+# SPDX-License-Identifier: GPL-2.0+\r\n+#\r\n+# Copyright (C) 2021, Chao-ying Fu \r\n+\r\n+config P8700_RISCV\r\n+\tbool\r\n+\tselect ARCH_EARLY_INIT_R\r\n+\timply CPU\r\n+\timply CPU_RISCV\r\n+\timply RISCV_ACLINT if (RISCV_MMODE || SPL_RISCV_MMODE)\r\n+\timply CMD_CPU\r\n+\timply SPL_CPU_SUPPORT\r\n+\timply SPL_OPENSBI\r\n+\timply SPL_LOAD_FIT\r\n+\r\n+config RISCV_CM_BASE\r\n+\thex \"RISCV CM Base Address\"\r\n+\tdefault 0x16100000\r\n+\thelp\r\n+\t The physical base address at which to map the Coherence Manager\r\n+\t Global Configuration Registers (GCRs).\r\ndiff --git a/arch/riscv/cpu/p8700/Makefile b/arch/riscv/cpu/p8700/Makefile\r\nnew file mode 100644\r\nindex 00000000000..04291375a29\r\n--- /dev/null\r\n+++ b/arch/riscv/cpu/p8700/Makefile\r\n@@ -0,0 +1,8 @@\r\n+# SPDX-License-Identifier: GPL-2.0+\r\n+#\r\n+# Copyright (C) 2021, Chao-ying Fu \r\n+\r\n+obj-y += cache.o\r\n+obj-y += cpu.o\r\n+obj-y += dram.o\r\n+obj-y += p8700.o\r\ndiff --git a/arch/riscv/cpu/p8700/cache.c b/arch/riscv/cpu/p8700/cache.c\r\nnew file mode 100644\r\nindex 00000000000..06e60156394\r\n--- /dev/null\r\n+++ b/arch/riscv/cpu/p8700/cache.c\r\n@@ -0,0 +1,93 @@\r\n+// SPDX-License-Identifier: GPL-2.0+\r\n+/*\r\n+ * Copyright (C) 2021, Chao-ying Fu \r\n+ */\r\n+\r\n+#include \r\n+#include \r\n+#include \r\n+#include \r\n+\r\n+#define MCACHE_BASE_INST 0xec0500f3\r\n+\r\n+/* NOTE: We force to use a0 in mcache to encode via .word.\r\n+ * 0xec0500f3 is a manually encoded custom RISC-V MCACHE instruction.\r\n+ * The bits [19:15] are set to 01010, selecting register x10 (a0)\r\n+ * as the source operand.\r\n+ * The bits [24:20] represent the 'op' field, which is currently set to 0.\r\n+ * Different cache operations are applied by OR-ing (op << 20) dynamically\r\n+ * to this base value.\r\n+ * Because of this encoding, the variable 'addr' is forced into register a0,\r\n+ * so that the MCACHE instruction uses the address in a0 as its operand.\r\n+ */\r\n+#define cache_loop(start, end, lsize, op) do {\t\t\t\t\\\r\n+\tconst __typeof__(lsize) __lsize = (lsize);\t\t\t\\\r\n+\tconst register void *addr asm(\"a0\") = (const void *)((start) & ~(__lsize - 1));\t\\\r\n+\tconst void *aend = (const void *)(((end) - 1) & ~(__lsize - 1));\t\\\r\n+\tfor (; addr <= aend; addr += __lsize)\t\t\t\t\\\r\n+\t\tasm volatile (\".word %0 | %1 # force to use %2\" \\\r\n+\t\t\t\t\t::\"i\"(MCACHE_BASE_INST), \"i\"((op) << 20), \"r\"(addr)); \\\r\n+} while (0)\r\n+\r\n+static unsigned long lsize;\r\n+static unsigned long l1d_total_size;\r\n+static unsigned long slsize;\r\n+\r\n+static void probe_cache_config(void)\r\n+{\r\n+\tlsize = 64;\r\n+\tl1d_total_size = 64 * 1024;\r\n+\r\n+\tint l2_config = 0;\r\n+\r\n+\tl2_config = readl((void __iomem *)(CM_BASE + GCR_L2_CONFIG_OFFSET));\r\n+\tint l2_line_size_info = (l2_config >> L2_LINE_SIZE_SHIFT)\r\n+\t\t\t\t& L2_LINE_SIZE_MASK;\r\n+\tslsize = (l2_line_size_info == 0) ? 0 : 1 << (l2_line_size_info + 1);\r\n+}\r\n+\r\n+void flush_dcache_range(unsigned long start, unsigned long end)\r\n+{\r\n+\tif (lsize == 0)\r\n+\t\tprobe_cache_config();\r\n+\r\n+\t/* aend will be miscalculated when size is zero, so we return here */\r\n+\tif (start >= end)\r\n+\t\treturn;\r\n+\r\n+\tcache_loop(start, end, lsize, HIT_WRITEBACK_INV_D);\r\n+\r\n+\t/* flush L2 cache */\r\n+\tif (slsize)\r\n+\t\tcache_loop(start, end, slsize, HIT_WRITEBACK_INV_SD);\r\n+\r\n+\t/* Instruction Hazard Barrier (IHB) — a hint-encoded SLLI (rd=0, rs1=0, imm=1).\r\n+\t * Ensures that all subsequent instruction fetches, including speculative ones,\r\n+\t * observe state changes from prior instructions.\r\n+\t * Required after MCACHE instructions when instruction fetch depends on cache ops.\r\n+\t */\r\n+\tasm volatile (\"slli x0,x0,1 # ihb\");\r\n+}\r\n+\r\n+void invalidate_dcache_range(unsigned long start, unsigned long end)\r\n+{\r\n+\tif (lsize == 0)\r\n+\t\tprobe_cache_config();\r\n+\r\n+\t/* aend will be miscalculated when size is zero, so we return here */\r\n+\tif (start >= end)\r\n+\t\treturn;\r\n+\r\n+\t/* invalidate L2 cache */\r\n+\tif (slsize)\r\n+\t\tcache_loop(start, end, slsize, HIT_INVALIDATE_SD);\r\n+\r\n+\tcache_loop(start, end, lsize, HIT_INVALIDATE_D);\r\n+\r\n+\t/* Instruction Hazard Barrier (IHB) — a hint-encoded SLLI (rd=0, rs1=0, imm=1).\r\n+\t * Ensures that all subsequent instruction fetches, including speculative ones,\r\n+\t * observe state changes from prior instructions.\r\n+\t * Required after MCACHE instructions when instruction fetch depends on cache ops.\r\n+\t */\r\n+\tasm volatile (\"slli x0,x0,1 # ihb\");\r\n+}\r\ndiff --git a/arch/riscv/cpu/p8700/cpu.c b/arch/riscv/cpu/p8700/cpu.c\r\nnew file mode 100644\r\nindex 00000000000..55b9f939f8e\r\n--- /dev/null\r\n+++ b/arch/riscv/cpu/p8700/cpu.c\r\n@@ -0,0 +1,105 @@\r\n+// SPDX-License-Identifier: GPL-2.0+\r\n+/*\r\n+ * Copyright (C) 2021, Chao-ying Fu \r\n+ */\r\n+\r\n+#include \r\n+#include \r\n+#include \r\n+#include \r\n+\r\n+static __noreturn void jump_to_addr(ulong addr)\r\n+{\r\n+\tasm volatile (\"jr %0\" :: \"r\"(addr) : \"memory\");\r\n+\t__builtin_unreachable();\r\n+}\r\n+\r\n+void harts_early_init(void)\r\n+{\r\n+\tif (!IS_ENABLED(CONFIG_RISCV_MMODE))\r\n+\t\treturn;\r\n+\r\n+\tulong hartid = csr_read(CSR_MHARTID);\r\n+\r\n+\t/* Wait for DDR3 calibration */\r\n+\twait_ddr_calib();\r\n+\r\n+\t/*\r\n+\t * Only mhartid[3:0] == 0 performs CM/GCR programming.\r\n+\t * Other harts skip CM/GCR setup and go straight to PMP/PMA setup.\r\n+\t */\r\n+\tif ((hartid & 0xFULL) == 0) {\r\n+\t\tulong cm_base = CM_BASE;\r\n+\t\tvoid __iomem *gcr_win = (void __iomem *)0x1fb80000;\r\n+\t\tulong cluster = (hartid >> MHARTID_CLUSTER_SHIFT) &\r\n+\t\t\t\tMHARTID_CLUSTER_MASK;\r\n+\r\n+\t\tcm_base += cluster << CM_BASE_CLUSTER_SHIFT;\r\n+\r\n+\t\tif ((hartid & 0xFFFFUL) == 0)\r\n+\t\t\twriteq(cm_base, gcr_win + GCR_BASE_OFFSET);\r\n+\r\n+\t\tulong core = (hartid >> MHARTID_CORE_SHIFT) & MHARTID_CORE_MASK;\r\n+\r\n+\t\t/* Enable coherency for the current core */\r\n+\t\tcm_base += core << CM_BASE_CORE_SHIFT;\r\n+\t\twriteq((u64)GCR_CL_COH_EN_EN,\r\n+\t\t (void __iomem *)(cm_base + P8700_GCR_C0_COH_EN));\r\n+\r\n+\t\t/*\r\n+\t\t * On hart 0, default PCIe DMA mapping should be the non-IOCU\r\n+\t\t * target.\r\n+\t\t */\r\n+\t\tif (hartid == 0)\r\n+\t\t\tsetup_pcie_dma_map();\r\n+\t}\r\n+\r\n+\t/* PMP setup */\r\n+\tcsr_write(pmpaddr1, 0x2fffffffUL);\r\n+\tcsr_write(pmpaddr2, 0x07ff7fffUL);\r\n+\tcsr_write(pmpaddr3, 0x07f3ffffUL);\r\n+\tcsr_write(pmpaddr4, 0x1fffffffffffffffUL);\r\n+\r\n+\tunsigned long pmpcfg = ((unsigned long)(PMP_NAPOT | PMP_R | PMP_W |\r\n+\t\t\t\t\t\tPMP_X) << 32) |\r\n+\t\t\t\t((unsigned long)(PMP_NAPOT | PMP_R |\r\n+\t\t\t\t\t\tPMP_X) << 24) |\r\n+\t\t\t\t((unsigned long)(PMP_NAPOT | PMP_R | PMP_W |\r\n+\t\t\t\t\t\tPMP_X) << 16) |\r\n+\t\t\t\t((unsigned long)(PMP_NAPOT | PMP_R | PMP_W |\r\n+\t\t\t\t\t\tPMP_X) << 8);\r\n+\r\n+\tcsr_write(pmpcfg0, pmpcfg);\r\n+\r\n+\t/* PMA/cache attributes */\r\n+\tulong pmacfg0;\r\n+\r\n+\tif (hartid == 0) {\r\n+\t\t/*\r\n+\t\t * Hart 0: cacheable for pma0, pma1, pma3; uncacheable for\r\n+\t\t * pma2, pma4.\r\n+\t\t */\r\n+\t\tpmacfg0 = ((unsigned long)CCA_CACHE_DISABLE << 32) |\r\n+\t\t\t((unsigned long)CCA_CACHE_ENABLE << 24) |\r\n+\t\t\t((unsigned long)CCA_CACHE_DISABLE << 16) |\r\n+\t\t\t((unsigned long)CCA_CACHE_ENABLE << 8) |\r\n+\t\t\t((unsigned long)CCA_CACHE_ENABLE);\r\n+\t} else {\r\n+\t\t/*\r\n+\t\t * Hart 1 or above: cacheable for pma0, pma1; uncacheable for\r\n+\t\t * pma2, pma3, pma4.\r\n+\t\t */\r\n+\t\tpmacfg0 = ((unsigned long)CCA_CACHE_DISABLE << 32) |\r\n+\t\t\t((unsigned long)CCA_CACHE_DISABLE << 24) |\r\n+\t\t\t((unsigned long)CCA_CACHE_DISABLE << 16) |\r\n+\t\t\t((unsigned long)CCA_CACHE_ENABLE << 8) |\r\n+\t\t\t((unsigned long)CCA_CACHE_ENABLE);\r\n+\t}\r\n+\r\n+\tasm volatile (\"csrw %0, %1\" :: \"i\"(CSR_PMACFG0), \"r\"(pmacfg0));\r\n+\tasm volatile (\"fence\" ::: \"memory\");\r\n+\r\n+\t/* Secondary harts: after early setup, jump to the common entry point */\r\n+\tif (hartid != 0)\r\n+\t\tjump_to_addr(CONFIG_SYS_LOAD_ADDR);\r\n+}\r\ndiff --git a/arch/riscv/cpu/p8700/dram.c b/arch/riscv/cpu/p8700/dram.c\r\nnew file mode 100644\r\nindex 00000000000..2b54326be39\r\n--- /dev/null\r\n+++ b/arch/riscv/cpu/p8700/dram.c\r\n@@ -0,0 +1,37 @@\r\n+// SPDX-License-Identifier: GPL-2.0+\r\n+/*\r\n+ * Copyright (C) 2018, Bin Meng \r\n+ */\r\n+\r\n+#include \r\n+#include \r\n+#include \r\n+\r\n+DECLARE_GLOBAL_DATA_PTR;\r\n+\r\n+int dram_init(void)\r\n+{\r\n+\treturn fdtdec_setup_mem_size_base();\r\n+}\r\n+\r\n+int dram_init_banksize(void)\r\n+{\r\n+\treturn fdtdec_setup_memory_banksize();\r\n+}\r\n+\r\n+phys_size_t board_get_usable_ram_top(phys_size_t total_size)\r\n+{\r\n+\tif (IS_ENABLED(CONFIG_64BIT)) {\r\n+\t\t/*\r\n+\t\t * Ensure that we run from first 4GB so that all\r\n+\t\t * addresses used by U-Boot are 32bit addresses.\r\n+\t\t *\r\n+\t\t * This in-turn ensures that 32bit DMA capable\r\n+\t\t * devices work fine because DMA mapping APIs will\r\n+\t\t * provide 32bit DMA addresses only.\r\n+\t\t */\r\n+\t\tif (gd->ram_top > SZ_4G)\r\n+\t\t\treturn SZ_4G;\r\n+\t}\r\n+\treturn gd->ram_top;\r\n+}\r\ndiff --git a/arch/riscv/cpu/p8700/p8700.c b/arch/riscv/cpu/p8700/p8700.c\r\nnew file mode 100644\r\nindex 00000000000..41d5547c511\r\n--- /dev/null\r\n+++ b/arch/riscv/cpu/p8700/p8700.c\r\n@@ -0,0 +1,12 @@\r\n+// SPDX-License-Identifier: GPL-2.0+\r\n+/*\r\n+ * Copyright (C) 2021, Chao-ying Fu \r\n+ */\r\n+\r\n+#include \r\n+#include \r\n+#include \r\n+\r\n+__weak void wait_ddr_calib(void) { }\r\n+\r\n+__weak void setup_pcie_dma_map(void) { }\r\ndiff --git a/arch/riscv/include/asm/arch-p8700/p8700.h b/arch/riscv/include/asm/arch-p8700/p8700.h\r\nnew file mode 100644\r\nindex 00000000000..d6cc125d76a\r\n--- /dev/null\r\n+++ b/arch/riscv/include/asm/arch-p8700/p8700.h\r\n@@ -0,0 +1,101 @@\r\n+/* SPDX-License-Identifier: GPL-2.0 */\r\n+/*\r\n+ * Copyright (C) 2021, Chao-ying Fu \r\n+ */\r\n+\r\n+#ifndef __P8700_H__\r\n+#define __P8700_H__\r\n+\r\n+#define CSR_MIPSCONFIG7\t\t0x7d7\r\n+#define CSR_PMACFG0\t\t\t0x7e0\r\n+\r\n+#define MHARTID_HART_SHIFT\t0\r\n+#define MHARTID_HART_MASK\t0xf\r\n+#define MHARTID_CORE_SHIFT\t4\r\n+#define MHARTID_CORE_MASK\t0xff\r\n+#define MHARTID_CLUSTER_SHIFT\t16\r\n+#define MHARTID_CLUSTER_MASK\t0xf\r\n+\r\n+#define MARCHID_UARCH_SHIFT\t0\r\n+#define MARCHID_UARCH_MASK\t0xff\r\n+#define MARCHID_CLASS_SHIFT\t8\r\n+#define MARCHID_CLASS_MASK\t0xff\r\n+#define MARCHID_CLASS_M\t\t0\r\n+#define MARCHID_CLASS_I\t\t1\r\n+#define MARCHID_CLASS_P\t\t2\r\n+\r\n+#define CM_BASE_CORE_SHIFT\t8\r\n+#define CM_BASE_CLUSTER_SHIFT\t19\r\n+\r\n+#define P8700_TIMER_ADDR\t0x16108050\r\n+\r\n+#define CCA_CACHE_ENABLE\t0\r\n+#define CCA_BUFFER_CACHE\t1\r\n+#define CCA_CACHE_DISABLE\t2\r\n+#define CCA_UNCACHE_ACC\t\t3\r\n+#define PMA_SPECULATION\t\t(0x1 << 3)\r\n+\r\n+#define L1_I_CACHE 0\r\n+#define L1_D_CACHE 1\r\n+#define L3_CACHE 2\r\n+#define L2_CACHE 3\r\n+\r\n+#define HIT_INVALIDATE 4\r\n+#define HIT_WRITEBACK_INV 5\r\n+\r\n+#define HIT_INVALIDATE_D ((HIT_INVALIDATE << 2) | L1_D_CACHE)\r\n+#define HIT_INVALIDATE_SD ((HIT_INVALIDATE << 2) | L2_CACHE)\r\n+#define HIT_WRITEBACK_INV_D ((HIT_WRITEBACK_INV << 2) | L1_D_CACHE)\r\n+#define HIT_WRITEBACK_INV_SD ((HIT_WRITEBACK_INV << 2) | L2_CACHE)\r\n+\r\n+#define L1D_LINE_SIZE_SHIFT\t10\r\n+#define L1D_LINE_SIZE_MASK\t0x7\r\n+\r\n+#define GCR_L2_CONFIG_OFFSET\t0x0130\r\n+#define L2_LINE_SIZE_SHIFT\t8\r\n+#define L2_LINE_SIZE_MASK\t0xf\r\n+\r\n+#define PMP_R\t\t\t0x01\r\n+#define PMP_W\t\t\t0x02\r\n+#define PMP_X\t\t\t0x04\r\n+#define PMP_TOR\t\t\t0x8\r\n+#define PMP_NA4\t\t\t0x10\r\n+#define PMP_NAPOT\t\t0x18\r\n+\r\n+#define CM_BASE\t\t\tCONFIG_RISCV_CM_BASE\r\n+#define CPC_BASE\t\t(CM_BASE + 0x8000)\r\n+\r\n+/* CPC Block offsets */\r\n+#define CPC_OFF_LOCAL\t\t0x2000\r\n+\r\n+#define CPC_PWRUP_CTL\t\t0x0030\r\n+\r\n+#define CPC_SYS_CONFIG\t\t0x0140\r\n+\r\n+#define CPC_Cx_CMD\t\t0x0000\r\n+#define CPC_Cx_CMD_RESET\t0x4\r\n+\r\n+#define P8700_GCR_C0_COH_EN\t0x20f8\r\n+#define P8700_GCR_C1_COH_EN\t0x21f8\r\n+#define P8700_GCR_C2_COH_EN\t0x22f8\r\n+#define P8700_GCR_C3_COH_EN\t0x23f8\r\n+#define P8700_GCR_C4_COH_EN\t0x24f8\r\n+#define P8700_GCR_C5_COH_EN\t0x25f8\r\n+\r\n+#define GCR_CL_COH_EN\t\t0x2008\r\n+#define GCR_CL_COH_EN_EN\t(0x1 << 0)\r\n+#define GCR_BASE_OFFSET\t\t0x0008\r\n+#define GIC_BASE_OFFSET\t\t0x0080\r\n+#define CPC_BASE_OFFSET\t\t0x0088\r\n+#define ENABLE\t\t\t0x1\r\n+#define COUNT_STOP\t\t(0x1 << 28)\r\n+#define GIC_LOCAL_SECTION_OFS\t0x8000\r\n+#define GIC_VL_MASK\t\t0x08\r\n+#define GIC_VL_RMASK\t\t0x0c\r\n+#define GIC_VL_SMASK\t\t0x10\r\n+#define GIC_VL_COMPARE_MAP\t0x44\r\n+\r\n+void wait_ddr_calib(void);\r\n+void setup_pcie_dma_map(void);\r\n+\r\n+#endif /* __P8700_H__ */\r\n","prefixes":["v7","1/7"]}