{"id":2224389,"url":"http://patchwork.ozlabs.org/api/patches/2224389/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417105618.3621-17-magnuskulke@linux.microsoft.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260417105618.3621-17-magnuskulke@linux.microsoft.com>","list_archive_url":null,"date":"2026-04-17T10:56:00","name":"[16/34] target/i386/mshv: migrate LAPIC state","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ffb1d136bf66c1d6e47806664bd27a02a2957ee9","submitter":{"id":90753,"url":"http://patchwork.ozlabs.org/api/people/90753/?format=json","name":"Magnus Kulke","email":"magnuskulke@linux.microsoft.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417105618.3621-17-magnuskulke@linux.microsoft.com/mbox/","series":[{"id":500310,"url":"http://patchwork.ozlabs.org/api/series/500310/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500310","date":"2026-04-17T10:55:44","name":"Add migration support to the MSHV accelerator","version":1,"mbox":"http://patchwork.ozlabs.org/series/500310/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224389/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224389/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=jh8ThyFs;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxsLc2mZtz1yD3\n\tfor ; Fri, 17 Apr 2026 20:58:32 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wDgtK-00020b-OX; Fri, 17 Apr 2026 06:57:42 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wDgtE-0001Nu-9K\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 06:57:38 -0400","from linux.microsoft.com ([13.77.154.182])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from ) id 1wDgtC-0001bh-78\n for qemu-devel@nongnu.org; Fri, 17 Apr 2026 06:57:35 -0400","from DESKTOP-TUU1E5L.fritz.box (p5086d620.dip0.t-ipconnect.de\n [80.134.214.32])\n by linux.microsoft.com (Postfix) with ESMTPSA id 2868620B7129;\n Fri, 17 Apr 2026 03:57:19 -0700 (PDT)"],"DKIM-Filter":"OpenDKIM Filter v2.11.0 linux.microsoft.com 2868620B7129","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1776423443;\n bh=n7/23i78ePWRFCNhXvpu2aDZEvpadavS9yPcaXyN5rw=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=jh8ThyFs/ODcR1xk4+8KIBEoaMRe8iwL0cLaJRiqYN3rE45XHIFYso3fkeTIGgf8o\n AHDZKir0CeUJdMf4VWKa7sA+W0qYNWWdtnwCyUo0TB5lElLHVJtiy9JOjaeB//YVDq\n XjvH394nRuh0skp4phxzIjGQx4zoYp4QfY9tnWBs=","From":"Magnus Kulke ","To":"qemu-devel@nongnu.org","Cc":"kvm@vger.kernel.org, Magnus Kulke ,\n Wei Liu , \"Michael S. Tsirkin\" ,\n\t=?utf-8?q?C=C3=A9dric_Le_Goater?= ,\n Zhao Liu ,\n Richard Henderson ,\n Paolo Bonzini , Wei Liu ,\n Magnus Kulke ,\n Alex Williamson ,\n Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= ,\n Marcelo Tosatti ","Subject":"[PATCH 16/34] target/i386/mshv: migrate LAPIC state","Date":"Fri, 17 Apr 2026 12:56:00 +0200","Message-Id":"<20260417105618.3621-17-magnuskulke@linux.microsoft.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260417105618.3621-1-magnuskulke@linux.microsoft.com>","References":"<20260417105618.3621-1-magnuskulke@linux.microsoft.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=13.77.154.182;\n envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com","X-Spam_score_int":"-42","X-Spam_score":"-4.3","X-Spam_bar":"----","X-Spam_report":"(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This change implements loading and storing the hyperv lapic state as\npart of the load/store routines for a vcpu.\n\nThe HyperV LAPIC is similar to the the split-irqchip in KVM, it will\nonly handle MSI/X interrupts. PIC and IOAPIC have to be handled in\nuserland.\n\nAn opaque blob is added to the APICCommonState, guarded behind a flag,\nhence it will be covered by a migration, as we declare VMSTATE_BUFFER\nfor the hv_lapic_state field.\n\nIn the future we might want to introduce a dedicated class for MSHV, that\nwould require us to wire up an IOAPIC delivery path to QEMU's userland\nemulation.\n\nSigned-off-by: Magnus Kulke \n---\n hw/intc/apic_common.c | 3 ++\n include/hw/i386/apic_internal.h | 5 +++\n target/i386/mshv/mshv-cpu.c | 61 +++++++++++++++++++++++++++++++--\n 3 files changed, 67 insertions(+), 2 deletions(-)","diff":"diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c\nindex bf4abc21d7..a7df870f1a 100644\n--- a/hw/intc/apic_common.c\n+++ b/hw/intc/apic_common.c\n@@ -380,6 +380,9 @@ static const VMStateDescription vmstate_apic_common = {\n VMSTATE_INT64(next_time, APICCommonState),\n VMSTATE_INT64(timer_expiry,\n APICCommonState), /* open-coded timer state */\n+#ifdef CONFIG_MSHV\n+ VMSTATE_BUFFER(hv_lapic_state, APICCommonState),\n+#endif\n VMSTATE_END_OF_LIST()\n },\n .subsections = (const VMStateDescription * const []) {\ndiff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_internal.h\nindex 0cb06bbc76..6d4ccca4e8 100644\n--- a/include/hw/i386/apic_internal.h\n+++ b/include/hw/i386/apic_internal.h\n@@ -23,6 +23,7 @@\n \n #include \"cpu.h\"\n #include \"hw/i386/apic.h\"\n+#include \"hw/hyperv/hvgdk_mini.h\"\n #include \"system/memory.h\"\n #include \"qemu/timer.h\"\n #include \"target/i386/cpu-qom.h\"\n@@ -188,6 +189,10 @@ struct APICCommonState {\n DeviceState *vapic;\n hwaddr vapic_paddr; /* note: persistence via kvmvapic */\n uint32_t extended_log_dest;\n+\n+#ifdef CONFIG_MSHV\n+ uint8_t hv_lapic_state[sizeof(struct hv_local_interrupt_controller_state)];\n+#endif\n };\n \n typedef struct VAPICState {\ndiff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c\nindex 12343acb01..22c962c5ac 100644\n--- a/target/i386/mshv/mshv-cpu.c\n+++ b/target/i386/mshv/mshv-cpu.c\n@@ -112,6 +112,25 @@ static int get_generic_regs(CPUState *cpu,\n struct hv_register_assoc *assocs,\n size_t n_regs);\n \n+static int get_lapic(CPUState *cpu)\n+{\n+ X86CPU *x86cpu = X86_CPU(cpu);\n+ APICCommonState *apic = APIC_COMMON(x86cpu->apic_state);\n+ int cpu_fd = mshv_vcpufd(cpu);\n+ int ret;\n+ struct hv_local_interrupt_controller_state lapic_state = { 0 };\n+\n+ ret = mshv_get_lapic(cpu_fd, &lapic_state);\n+ if (ret < 0) {\n+ error_report(\"failed to get lapic state\");\n+ return -1;\n+ }\n+\n+ memcpy(&apic->hv_lapic_state, &lapic_state, sizeof(lapic_state));\n+\n+ return 0;\n+}\n+\n static void populate_fpu(const hv_register_assoc *assocs, X86CPU *x86cpu)\n {\n union hv_register_value value;\n@@ -559,6 +578,11 @@ int mshv_arch_load_vcpu_state(CPUState *cpu)\n return ret;\n }\n \n+ ret = get_lapic(cpu);\n+ if (ret < 0) {\n+ return ret;\n+ }\n+\n return 0;\n }\n \n@@ -926,9 +950,11 @@ static uint32_t set_apic_delivery_mode(uint32_t reg, uint32_t mode)\n \n static int init_lint(const CPUState *cpu)\n {\n- int ret;\n+ X86CPU *x86cpu = X86_CPU(cpu);\n+ APICCommonState *apic = APIC_COMMON(x86cpu->apic_state);\n uint32_t *lvt_lint0, *lvt_lint1;\n int cpu_fd = mshv_vcpufd(cpu);\n+ int ret;\n \n struct hv_local_interrupt_controller_state lapic_state = { 0 };\n ret = mshv_get_lapic(cpu_fd, &lapic_state);\n@@ -944,7 +970,32 @@ static int init_lint(const CPUState *cpu)\n \n /* TODO: should we skip setting lapic if the values are the same? */\n \n- return mshv_set_lapic(cpu_fd, &lapic_state);\n+ ret = mshv_set_lapic(cpu_fd, &lapic_state);\n+ if (ret < 0) {\n+ return -1;\n+ }\n+\n+ memcpy(apic->hv_lapic_state, &lapic_state, sizeof(lapic_state));\n+\n+ return 0;\n+}\n+\n+static int set_lapic(const CPUState *cpu)\n+{\n+ X86CPU *x86cpu = X86_CPU(cpu);\n+ APICCommonState *apic = APIC_COMMON(x86cpu->apic_state);\n+ int cpu_fd = mshv_vcpufd(cpu);\n+ int ret;\n+\n+ struct hv_local_interrupt_controller_state lapic_state = { 0 };\n+ memcpy(&lapic_state, &apic->hv_lapic_state, sizeof(lapic_state));\n+ ret = mshv_set_lapic(cpu_fd, &lapic_state);\n+ if (ret < 0) {\n+ error_report(\"failed to set lapic\");\n+ return -1;\n+ }\n+\n+ return 0;\n }\n \n int mshv_arch_store_vcpu_state(const CPUState *cpu)\n@@ -971,6 +1022,12 @@ int mshv_arch_store_vcpu_state(const CPUState *cpu)\n return ret;\n }\n \n+ /* INVARIANT: special regs (APIC_BASE) must be restored before LAPIC */\n+ ret = set_lapic(cpu);\n+ if (ret < 0) {\n+ return ret;\n+ }\n+\n return 0;\n }\n \n","prefixes":["16/34"]}