{"id":2224361,"url":"http://patchwork.ozlabs.org/api/patches/2224361/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417104652.17857-2-xiaoou@iscas.ac.cn/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260417104652.17857-2-xiaoou@iscas.ac.cn>","list_archive_url":null,"date":"2026-04-17T10:46:38","name":"[01/14] target/riscv: rvp: Add option defines and dependency check for packed simd extension","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"028108d997575cd281ef6c29e32bed3fb0c3c49b","submitter":{"id":89843,"url":"http://patchwork.ozlabs.org/api/people/89843/?format=json","name":"Molly Chen","email":"xiaoou@iscas.ac.cn"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417104652.17857-2-xiaoou@iscas.ac.cn/mbox/","series":[{"id":500307,"url":"http://patchwork.ozlabs.org/api/series/500307/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500307","date":"2026-04-17T10:46:37","name":"target/riscv: add support for RISC-V P extension (v0.20 draft)","version":1,"mbox":"http://patchwork.ozlabs.org/series/500307/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224361/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224361/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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envelope-from=xiaoou@iscas.ac.cn;\n helo=cstnet.cn","X-Spam_score_int":"-21","X-Spam_score":"-2.2","X-Spam_bar":"--","X-Spam_report":"(-2.2 / 5.0 requ) BAYES_00=-1.9, HK_RANDOM_ENVFROM=0.998,\n HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Co-Authored by: Yin Zhang \nCo-Authored by: Dajun Huang \nCo-Authored by: Zhiyuan Yang \n\nSigned-off-by: Molly Chen \n---\n target/riscv/cpu.c | 5 +++--\n target/riscv/cpu.h | 1 +\n target/riscv/tcg/tcg-cpu.c | 16 ++++++++++++++++\n 3 files changed, 20 insertions(+), 2 deletions(-)","diff":"diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 72c6f4f0f1..c630faa892 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -41,7 +41,7 @@\n /* RISC-V CPU definitions */\n static const char riscv_single_letter_exts[] = \"IEMAFDQCBPVH\";\n const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,\n- RVC, RVS, RVU, RVH, RVG, RVB, 0};\n+ RVC, RVS, RVU, RVH, RVG, RVB, RVP, 0};\n \n /*\n * From vector_helper.c\n@@ -1172,7 +1172,8 @@ static const MISAExtInfo misa_ext_info_arr[] = {\n MISA_EXT_INFO(RVH, \"h\", \"Hypervisor\"),\n MISA_EXT_INFO(RVV, \"v\", \"Vector operations\"),\n MISA_EXT_INFO(RVG, \"g\", \"General purpose (IMAFD_Zicsr_Zifencei)\"),\n- MISA_EXT_INFO(RVB, \"b\", \"Bit manipulation (Zba_Zbb_Zbs)\")\n+ MISA_EXT_INFO(RVB, \"b\", \"Bit manipulation (Zba_Zbb_Zbs)\"),\n+ MISA_EXT_INFO(RVP, \"x-p\", \"Packed-SIMD instructions\")\n };\n \n static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)\ndiff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 4c0676ed53..e08f57d282 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -69,6 +69,7 @@ typedef struct CPUArchState CPURISCVState;\n #define RVH RV('H')\n #define RVG RV('G')\n #define RVB RV('B')\n+#define RVP RV('P')\n \n extern const uint32_t misa_bits[];\n const char *riscv_get_misa_ext_name(uint32_t bit);\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex f3f7808895..4545ae721c 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -601,6 +601,11 @@ static void riscv_cpu_validate_b(RISCVCPU *cpu)\n }\n }\n \n+static void riscv_cpu_validate_p(RISCVCPU *cpu)\n+{\n+ /* Enable sub-extensions here. Do nothing for now. */\n+}\n+\n /*\n * Check consistency between chosen extensions while setting\n * cpu->cfg accordingly.\n@@ -619,6 +624,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)\n riscv_cpu_validate_b(cpu);\n }\n \n+ if (riscv_has_ext(env, RVP)) {\n+ riscv_cpu_validate_p(cpu);\n+ }\n+\n if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {\n error_setg(errp,\n \"I and E extensions are incompatible\");\n@@ -683,6 +692,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)\n return;\n }\n \n+ if (riscv_has_ext(env, RVP) &&\n+ !(cpu->cfg.ext_zba && cpu->cfg.ext_zbb && cpu->cfg.ext_zbkb)) {\n+ error_setg(errp, \"P extension requires zba, zbb and zbkb extensions\");\n+ return;\n+ }\n+\n riscv_cpu_validate_v(env, &cpu->cfg, &local_err);\n if (local_err != NULL) {\n error_propagate(errp, local_err);\n@@ -1413,6 +1428,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {\n MISA_CFG(RVV, false),\n MISA_CFG(RVG, false),\n MISA_CFG(RVB, false),\n+ MISA_CFG(RVP, false),\n };\n \n /*\n","prefixes":["01/14"]}