{"id":2224223,"url":"http://patchwork.ozlabs.org/api/patches/2224223/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417042620.35329-4-philmd@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260417042620.35329-4-philmd@linaro.org>","list_archive_url":null,"date":"2026-04-17T04:26:18","name":"[v6,3/4] target/mips: Inline translator_ld[uw,l,q]() calls","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"7748da82a50c4f2b86e59fed23f00f899055c248","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417042620.35329-4-philmd@linaro.org/mbox/","series":[{"id":500237,"url":"http://patchwork.ozlabs.org/api/series/500237/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500237","date":"2026-04-17T04:26:15","name":"target/mips: Use probe_access_full() in Atomic Load/Store helpers","version":6,"mbox":"http://patchwork.ozlabs.org/series/500237/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224223/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224223/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google 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(PDT)","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","To":"qemu-devel@nongnu.org","Cc":"Jiaxun Yang ,\n Aleksandar Rikalo , Aurelien Jarno ,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ,\n Richard Henderson ","Subject":"[PATCH v6 3/4] target/mips: Inline translator_ld[uw,l,q]() calls","Date":"Fri, 17 Apr 2026 06:26:18 +0200","Message-ID":"<20260417042620.35329-4-philmd@linaro.org>","X-Mailer":"git-send-email 2.53.0","In-Reply-To":"<20260417042620.35329-1-philmd@linaro.org>","References":"<20260417042620.35329-1-philmd@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::42a;\n envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"In preparation of removing the translator_ld[uw,l,q]() methods,\ninline them for the MIPS target, expanding MO_TE by a runtime\ncheck on mo_endian(ctx).\n\nMechanical change using the following Coccinelle 'spatch' script:\n\n @@\n expression env, db, pc;\n @@\n (\n - translator_lduw(env, db, pc)\n + translator_lduw_end(env, db, pc, mo_endian(ctx))\n |\n - translator_ldl(env, db, pc)\n + translator_ldl_end(env, db, pc, mo_endian(ctx))\n |\n - translator_ldq(env, db, pc)\n + translator_ldq_end(env, db, pc, mo_endian(ctx))\n )\n\nSigned-off-by: Philippe Mathieu-Daudé \n---\n target/mips/tcg/translate.c | 12 ++++++++----\n target/mips/tcg/micromips_translate.c.inc | 2 +-\n target/mips/tcg/mips16e_translate.c.inc | 6 ++++--\n target/mips/tcg/nanomips_translate.c.inc | 5 +++--\n 4 files changed, 16 insertions(+), 9 deletions(-)","diff":"diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c\nindex 4889bd1e518..8b570188538 100644\n--- a/target/mips/tcg/translate.c\n+++ b/target/mips/tcg/translate.c\n@@ -15147,17 +15147,21 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)\n \n is_slot = ctx->hflags & MIPS_HFLAG_BMASK;\n if (ctx->insn_flags & ISA_NANOMIPS32) {\n- ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);\n+ ctx->opcode = translator_lduw_end(env, &ctx->base, ctx->base.pc_next,\n+ mo_endian(ctx));\n insn_bytes = decode_isa_nanomips(env, ctx);\n } else if (!(ctx->hflags & MIPS_HFLAG_M16)) {\n- ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);\n+ ctx->opcode = translator_ldl_end(env, &ctx->base, ctx->base.pc_next,\n+ mo_endian(ctx));\n insn_bytes = 4;\n decode_opc(env, ctx);\n } else if (ctx->insn_flags & ASE_MICROMIPS) {\n- ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);\n+ ctx->opcode = translator_lduw_end(env, &ctx->base, ctx->base.pc_next,\n+ mo_endian(ctx));\n insn_bytes = decode_isa_micromips(env, ctx);\n } else if (ctx->insn_flags & ASE_MIPS16) {\n- ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);\n+ ctx->opcode = translator_lduw_end(env, &ctx->base, ctx->base.pc_next,\n+ mo_endian(ctx));\n insn_bytes = decode_ase_mips16e(env, ctx);\n } else {\n gen_reserved_instruction(ctx);\ndiff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc\nindex 8fda7c8a214..b38c37194ad 100644\n--- a/target/mips/tcg/micromips_translate.c.inc\n+++ b/target/mips/tcg/micromips_translate.c.inc\n@@ -1623,7 +1623,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)\n uint32_t op, minor, minor2, mips32_op;\n uint32_t cond, fmt, cc;\n \n- insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);\n+ insn = translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 2, mo_endian(ctx));\n ctx->opcode = (ctx->opcode << 16) | insn;\n \n rt = (ctx->opcode >> 21) & 0x1f;\ndiff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc\nindex 97da3456ea5..beb5b04ea29 100644\n--- a/target/mips/tcg/mips16e_translate.c.inc\n+++ b/target/mips/tcg/mips16e_translate.c.inc\n@@ -453,7 +453,8 @@ static void decode_i64_mips16(DisasContext *ctx,\n \n static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)\n {\n- int extend = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);\n+ int extend = translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 2,\n+ mo_endian(ctx));\n int op, rx, ry, funct, sa;\n int16_t imm, offset;\n \n@@ -686,7 +687,8 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)\n /* No delay slot, so just process as a normal instruction */\n break;\n case M16_OPC_JAL:\n- offset = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);\n+ offset = translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 2,\n+ mo_endian(ctx));\n offset = (((ctx->opcode & 0x1f) << 21)\n | ((ctx->opcode >> 5) & 0x1f) << 16\n | offset) << 2;\ndiff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc\nindex 9d4e0bee81f..4b0b01ba37a 100644\n--- a/target/mips/tcg/nanomips_translate.c.inc\n+++ b/target/mips/tcg/nanomips_translate.c.inc\n@@ -3551,7 +3551,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n int offset;\n int imm;\n \n- insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);\n+ insn = translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 2, mo_endian(ctx));\n ctx->opcode = (ctx->opcode << 16) | insn;\n \n rt = extract32(ctx->opcode, 21, 5);\n@@ -3665,7 +3665,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)\n break;\n case NM_P48I:\n {\n- insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 4);\n+ insn = translator_lduw_end(env, &ctx->base, ctx->base.pc_next + 4,\n+ mo_endian(ctx));\n target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16;\n switch (extract32(ctx->opcode, 16, 5)) {\n case NM_LI48:\n","prefixes":["v6","3/4"]}