{"id":2224211,"url":"http://patchwork.ozlabs.org/api/patches/2224211/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417035734.32334-4-philmd@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260417035734.32334-4-philmd@linaro.org>","list_archive_url":null,"date":"2026-04-17T03:57:33","name":"[v5,3/4] target/mips: Inline cpu_ld/st_mmuidx_ra() calls in LD/ST Multiple","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f26933583c3455128e0c3028e4d3c113e4ab1ded","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417035734.32334-4-philmd@linaro.org/mbox/","series":[{"id":500232,"url":"http://patchwork.ozlabs.org/api/series/500232/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500232","date":"2026-04-17T03:57:30","name":"target/mips: Replace cpu_ld/st_mmuidx_ra() calls in LD/ST Multiple","version":5,"mbox":"http://patchwork.ozlabs.org/series/500232/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224211/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224211/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=nGhfy2f0;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32e;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"In preparation of removing the cpu_ld*_mmuidx_ra() and\ncpu_st*_mmuidx_ra() calls, inline them. Expand MO_TE to\nmo_endian_env(env) in gen_ldst_multiple().\n\nSigned-off-by: Philippe Mathieu-Daudé \nReviewed-by: Richard Henderson \n---\n target/mips/tcg/ldst_helper.c | 34 +++++++++++------------\n target/mips/tcg/micromips_translate.c.inc | 2 ++\n 2 files changed, 18 insertions(+), 18 deletions(-)","diff":"diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c\nindex 07a4aa99bae..b3ea4f05192 100644\n--- a/target/mips/tcg/ldst_helper.c\n+++ b/target/mips/tcg/ldst_helper.c\n@@ -227,21 +227,20 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,\n uint32_t memop_idx)\n {\n MemOpIdx oi = memop_idx;\n- unsigned mem_idx = get_mmuidx(oi);\n unsigned base_reglist = reglist & 0xf;\n bool do_r31 = reglist & 0x10;\n+ target_ulong *gpr = env->active_tc.gpr;\n+ uintptr_t ra = GETPC();\n \n if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {\n for (unsigned i = 0; i < base_reglist; i++) {\n- env->active_tc.gpr[multiple_regs[i]] =\n- (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());\n+ gpr[multiple_regs[i]] = (target_long)cpu_ldl_mmu(env, addr, oi, ra);\n addr += 4;\n }\n }\n \n if (do_r31) {\n- env->active_tc.gpr[31] =\n- (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());\n+ gpr[31] = (target_long)cpu_ldl_mmu(env, addr, oi, ra);\n }\n }\n \n@@ -249,20 +248,20 @@ void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,\n uint32_t memop_idx)\n {\n MemOpIdx oi = memop_idx;\n- unsigned mem_idx = get_mmuidx(oi);\n unsigned base_reglist = reglist & 0xf;\n bool do_r31 = reglist & 0x10;\n+ target_ulong *gpr = env->active_tc.gpr;\n+ uintptr_t ra = GETPC();\n \n if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {\n for (unsigned i = 0; i < base_reglist; i++) {\n- cpu_stl_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],\n- mem_idx, GETPC());\n+ cpu_stl_mmu(env, addr, gpr[multiple_regs[i]], oi, ra);\n addr += 4;\n }\n }\n \n if (do_r31) {\n- cpu_stl_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());\n+ cpu_stl_mmu(env, addr, gpr[31], oi, ra);\n }\n }\n \n@@ -271,21 +270,20 @@ void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,\n uint32_t memop_idx)\n {\n MemOpIdx oi = memop_idx;\n- unsigned mem_idx = get_mmuidx(oi);\n unsigned base_reglist = reglist & 0xf;\n bool do_r31 = reglist & 0x10;\n+ target_ulong *gpr = env->active_tc.gpr;\n+ uintptr_t ra = GETPC();\n \n if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {\n for (unsigned i = 0; i < base_reglist; i++) {\n- env->active_tc.gpr[multiple_regs[i]] =\n- cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());\n+ gpr[multiple_regs[i]] = cpu_ldq_mmu(env, addr, oi, ra);\n addr += 8;\n }\n }\n \n if (do_r31) {\n- env->active_tc.gpr[31] =\n- cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());\n+ gpr[31] = cpu_ldq_mmu(env, addr, oi, ra);\n }\n }\n \n@@ -293,20 +291,20 @@ void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,\n uint32_t memop_idx)\n {\n MemOpIdx oi = memop_idx;\n- unsigned mem_idx = get_mmuidx(oi);\n unsigned base_reglist = reglist & 0xf;\n bool do_r31 = reglist & 0x10;\n+ target_ulong *gpr = env->active_tc.gpr;\n+ uintptr_t ra = GETPC();\n \n if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {\n for (unsigned i = 0; i < base_reglist; i++) {\n- cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],\n- mem_idx, GETPC());\n+ cpu_stq_mmu(env, addr, gpr[multiple_regs[i]], oi, ra);\n addr += 8;\n }\n }\n \n if (do_r31) {\n- cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());\n+ cpu_stq_mmu(env, addr, gpr[31], oi, ra);\n }\n }\n \ndiff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc\nindex 4dca11b84b4..fb107eb91fe 100644\n--- a/target/mips/tcg/micromips_translate.c.inc\n+++ b/target/mips/tcg/micromips_translate.c.inc\n@@ -701,6 +701,8 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,\n return;\n }\n \n+ mop |= mo_endian(ctx);\n+\n t0 = tcg_temp_new();\n \n gen_base_offset_addr(ctx, t0, base, offset);\n","prefixes":["v5","3/4"]}