{"id":2224163,"url":"http://patchwork.ozlabs.org/api/patches/2224163/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260417022104.3973576-3-ycliang@andestech.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260417022104.3973576-3-ycliang@andestech.com>","list_archive_url":null,"date":"2026-04-17T02:20:58","name":"[2/8] spi: atcspi200: Improve clock configuration and divider logic","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3ab721dd06dc2b6f7f362ab034be9cc47eddc717","submitter":{"id":79234,"url":"http://patchwork.ozlabs.org/api/people/79234/?format=json","name":"Leo Yu-Chi Liang","email":"ycliang@andestech.com"},"delegate":{"id":17739,"url":"http://patchwork.ozlabs.org/api/users/17739/?format=json","username":"jagan","first_name":"Jagannadha Sutradharudu","last_name":"Teki","email":"jagannadh.teki@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260417022104.3973576-3-ycliang@andestech.com/mbox/","series":[{"id":500221,"url":"http://patchwork.ozlabs.org/api/series/500221/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=500221","date":"2026-04-17T02:20:56","name":"spi: atcspi200: Modernize driver and add spi-mem + data merge support","version":1,"mbox":"http://patchwork.ozlabs.org/series/500221/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224163/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224163/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=fail (p=reject dis=none) header.from=andestech.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de; dmarc=fail (p=reject dis=none)\n header.from=andestech.com","phobos.denx.de;\n spf=pass smtp.mailfrom=ycliang@andestech.com"],"Received":["from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxdtT6JCkz1yGt\n\tfor ; Fri, 17 Apr 2026 12:21:53 +1000 (AEST)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 545868421D;\n\tFri, 17 Apr 2026 04:21:36 +0200 (CEST)","by phobos.denx.de (Postfix, from userid 109)\n id ACB608423E; Fri, 17 Apr 2026 04:21:34 +0200 (CEST)","from Atcsqr.andestech.com (unknown [60.248.187.195])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id ECA448421D\n for ; Fri, 17 Apr 2026 04:21:31 +0200 (CEST)","from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134])\n by Atcsqr.andestech.com with ESMTP id 63H2LAtO015784;\n Fri, 17 Apr 2026 10:21:10 +0800 (+08)\n (envelope-from ycliang@andestech.com)","from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com\n (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 17 Apr\n 2026 10:21:10 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-1.1 required=5.0 tests=BAYES_00,\n RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,\n RCVD_IN_VALIDITY_RPBL_BLOCKED,RDNS_NONE,SPF_HELO_NONE,SPF_PASS\n autolearn=no autolearn_force=no version=3.4.2","From":"Leo Yu-Chi Liang ","To":"","CC":"Tom Rini , Vignesh R , \"Takahiro\n Kuwano\" , Jagan Teki\n , , CL Chin-Long Wang\n ","Subject":"[PATCH 2/8] spi: atcspi200: Improve clock configuration and divider\n logic","Date":"Fri, 17 Apr 2026 10:20:58 +0800","Message-ID":"<20260417022104.3973576-3-ycliang@andestech.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260417022104.3973576-1-ycliang@andestech.com>","References":"<20260417022104.3973576-1-ycliang@andestech.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-Originating-IP":"[10.0.15.183]","X-ClientProxiedBy":"ATCPCS33.andestech.com (10.0.1.100) To\n ATCPCS34.andestech.com (10.0.1.134)","X-DKIM-Results":"atcpcs34.andestech.com; dkim=none;","X-DNSRBL":"","X-MAIL":"Atcsqr.andestech.com 63H2LAtO015784","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"- Add default clock source (100 MHz) and max frequency (40 MHz)\n fallbacks when DT properties are missing\n- Read spi-max-frequency from DT to cap the operating frequency\n- Use improved round-up divider formula that selects the closest\n available frequency not exceeding the target\n- Add SCLK_DIV_BYPASS (0xFF) and SCLK_DIV_MAX (0xFE) constants\n- Remove mtiming field and timing restore in stop(), which was\n incorrectly resetting clock settings after every transfer\n- Change clock fields from ulong to unsigned int\n\nSigned-off-by: CL Chin-Long Wang \nSigned-off-by: Leo Yu-Chi Liang \n---\n drivers/spi/atcspi200_spi.c | 57 +++++++++++++++++++++++--------------\n 1 file changed, 36 insertions(+), 21 deletions(-)","diff":"diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c\nindex 8cae96ee23c..33cf7583581 100644\n--- a/drivers/spi/atcspi200_spi.c\n+++ b/drivers/spi/atcspi200_spi.c\n@@ -18,6 +18,8 @@\n #define MAX_TRANSFER_LEN\t512\n #define CHUNK_SIZE\t\t1\n #define SPI_TIMEOUT\t\t0x100000\n+#define SPI_DEF_SRC_CLK\t\t100000000\n+#define SPI_DEF_MAX_CLK\t\t40000000\n \n /* Register offsets */\n #define ATCSPI200_REG_FORMAT\t0x10\n@@ -61,15 +63,17 @@\n \n /* TIMING register fields */\n #define SCLK_DIV_MASK\t\tGENMASK(7, 0)\n+#define SCLK_DIV_BYPASS\t\t0xFF\n+#define SCLK_DIV_MAX\t\t0xFE\n \n struct atcspi200_priv {\n \tvoid\t\t*regs;\n \tint\t\tto;\n \tunsigned int\tfreq;\n-\tulong\t\tclock;\n+\tunsigned int\tsrc_clk;\n+\tunsigned int\tmax_clk;\n \tunsigned int\tmode;\n \tu8\t\tnum_cs;\n-\tunsigned int\tmtiming;\n \tsize_t\t\tcmd_len;\n \tu8\t\tcmd_buf[16];\n \tsize_t\t\tdata_len;\n@@ -93,22 +97,28 @@ static inline void atcspi200_write(struct atcspi200_priv *priv, u32 offset,\n static int atcspi200_hw_set_speed(struct atcspi200_priv *priv)\n {\n \tu32 tm;\n-\tu8 div;\n+\tu32 div;\n+\tu32 spi_sclk;\n \n-\ttm = atcspi200_read(priv, ATCSPI200_REG_TIMING);\n-\ttm &= ~SCLK_DIV_MASK;\n+\ttm = atcspi200_read(priv, ATCSPI200_REG_TIMING) & ~SCLK_DIV_MASK;\n \n-\tif (priv->freq >= priv->clock) {\n-\t\tdiv = 0xff;\n+\tspi_sclk = min(priv->freq, priv->max_clk);\n+\n+\t/*\n+\t * SCLK_DIV = 0xFF bypasses the divider, giving SCLK = src_clk.\n+\t * Otherwise SCLK = src_clk / (2 * (SCLK_DIV + 1)).\n+\t */\n+\tif (spi_sclk >= priv->src_clk) {\n+\t\tdiv = SCLK_DIV_BYPASS;\n \t} else {\n-\t\tfor (div = 0; div < 0xff; div++) {\n-\t\t\tif (priv->freq >= priv->clock / (2 * (div + 1)))\n-\t\t\t\tbreak;\n+\t\tdiv = DIV_ROUND_UP(priv->src_clk, spi_sclk * 2) - 1;\n+\t\tif (div > SCLK_DIV_MAX) {\n+\t\t\tpr_err(\"Unsupported SPI clock %u\\n\", spi_sclk);\n+\t\t\treturn -EINVAL;\n \t\t}\n \t}\n \n-\ttm |= div;\n-\tatcspi200_write(priv, ATCSPI200_REG_TIMING, tm);\n+\tatcspi200_write(priv, ATCSPI200_REG_TIMING, tm | div);\n \n \treturn 0;\n }\n@@ -166,7 +176,6 @@ static int atcspi200_hw_start(struct atcspi200_priv *priv)\n \n static int atcspi200_hw_stop(struct atcspi200_priv *priv)\n {\n-\tatcspi200_write(priv, ATCSPI200_REG_TIMING, priv->mtiming);\n \twhile ((atcspi200_read(priv, ATCSPI200_REG_STATUS) & SPIBSY) &&\n \t priv->to--)\n \t\tif (!priv->to)\n@@ -353,14 +362,21 @@ static int atcspi200_spi_get_clk(struct udevice *bus)\n \tint ret;\n \n \tret = clk_get_by_index(bus, 0, &clk);\n-\tif (ret)\n-\t\treturn -EINVAL;\n-\n-\tclk_rate = clk_get_rate(&clk);\n-\tif (!clk_rate)\n-\t\treturn -EINVAL;\n+\tif (ret) {\n+\t\tdev_warn(bus, \"no clock node, using default %d Hz\\n\",\n+\t\t\t SPI_DEF_SRC_CLK);\n+\t\tpriv->src_clk = SPI_DEF_SRC_CLK;\n+\t} else {\n+\t\tclk_rate = clk_get_rate(&clk);\n+\t\tif (!clk_rate) {\n+\t\t\tdev_err(bus, \"invalid clock rate\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tpriv->src_clk = clk_rate;\n+\t}\n \n-\tpriv->clock = clk_rate;\n+\tpriv->max_clk = dev_read_u32_default(bus, \"spi-max-frequency\",\n+\t\t\t\t\t SPI_DEF_MAX_CLK);\n \n \treturn 0;\n }\n@@ -371,7 +387,6 @@ static int atcspi200_spi_probe(struct udevice *bus)\n \n \tpriv->to = SPI_TIMEOUT;\n \tpriv->max_transfer_length = MAX_TRANSFER_LEN;\n-\tpriv->mtiming = atcspi200_read(priv, ATCSPI200_REG_TIMING);\n \tatcspi200_spi_get_clk(bus);\n \n \treturn 0;\n","prefixes":["2/8"]}