{"id":2224149,"url":"http://patchwork.ozlabs.org/api/patches/2224149/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/b4344b8d30a75d5d8d0acdbd9f038d9cddb4147d.1776381841.git.nicolinc@nvidia.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-04-16T23:28:39","name":"[v3,10/11] iommu/arm-smmu-v3: Introduce master->ats_broken flag","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"25dbf9028d6e98c445db0b15bae0c0f2a89c75b9","submitter":{"id":82183,"url":"http://patchwork.ozlabs.org/api/people/82183/?format=json","name":"Nicolin Chen","email":"nicolinc@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/b4344b8d30a75d5d8d0acdbd9f038d9cddb4147d.1776381841.git.nicolinc@nvidia.com/mbox/","series":[{"id":500217,"url":"http://patchwork.ozlabs.org/api/series/500217/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=500217","date":"2026-04-16T23:28:31","name":"iommu/arm-smmu-v3: Quarantine device upon ATC invalidation timeout","version":3,"mbox":"http://patchwork.ozlabs.org/series/500217/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224149/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224149/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=DvwbMDdR;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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Wysocki\" , Len Brown ,\n\tPranjal Shrivastava , Mostafa Saleh ,\n\tLu Baolu , Kevin Tian ,\n\t, ,\n\t, ,\n\t, , Shuai Xue\n\t","Subject":"[PATCH v3 10/11] iommu/arm-smmu-v3: Introduce master->ats_broken flag","Date":"Thu, 16 Apr 2026 16:28:39 -0700","Message-ID":"\n ","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"","References":"","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-NV-OnPremToCloud":"ExternallySecured","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"CO1PEPF00012E80:EE_|BL1PR12MB5996:EE_","X-MS-Office365-Filtering-Correlation-Id":"7f18b5f4-6b3c-493e-4433-08de9c10198a","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"\n\tBCL:0;ARA:13230040|1800799024|82310400026|7416014|36860700016|376014|18002099003|22082099003|56012099003|11006099003;","X-Microsoft-Antispam-Message-Info":"\n\th8/wZ0WnMrzk7tyGjFrjO44ziq1JtowcO8qrJvr2liKfeFIl114o/vSEYvKHvOH7CMxYCs3j9x6GzC+IJG5CV/Z3lBQ5ZaHmb4j6tSup1fB+3pB/E2QPQFAe2H640lq24QpuMwGy195eyM832Qm6yWCo1RnK0FmswVCoccDeZ275ilG+NPK3eYxAm1ha3M3mM/o+6jr3cBzICfEQSAdkOod1p3jX3Wl4ISlBYhz70R7lCQmFbqaXYBCXn1Y6yW3Xs8qrmfeLn8oxcxGYWdO8/qby0D7mhQ2fshAHClRL25tUkIlgCPqz7Wc0Y5jluRzGUHhMeHr7eWNc/E4BPLs+hdYx1xymFOiRQ0hANannaJ4DveoFZ4ZfBPUhg+kpzJHM9VBj8WEytHAUlMeGsbuYU+C6fy7bNv+tthojQGsgg7k18qIl0UrJkgy/JQYEgdG3NJiw7POr8cc+naxG+Avi/dJSoOu60mqS0dcXfhcPGMPiCFmc5peDHse9TXp0olDkkhOqyWMqe0dHIQj+8twBfj5UT6iH0KeGze0/3rIQCAj5cCcj6kOipDUTEyMfOIhqXsYXoye8emBl3VngcEGUek/tWZEIK57LSlg+EJ6W35Q2A6T4O/8JpskHtyDAKQfCDQeQh8WXDt22A1IKfPm1t9ZdmEI5vjtlhVS3xZ8zikvPr0lZ4yuVrntOsXHw6bGrpXVNBpG+2rbjqQGajB0hdcdR+JFutXzvqVKp+FDjnwEpHgS6lCP2xTjDMBOtoyYg/4PA6nZvL6oxRSpuIegoHg==","X-Forefront-Antispam-Report":"\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(7416014)(36860700016)(376014)(18002099003)(22082099003)(56012099003)(11006099003);DIR:OUT;SFP:1101;","X-MS-Exchange-AntiSpam-MessageData-ChunkCount":"1","X-MS-Exchange-AntiSpam-MessageData-0":"\n\tvpJJ+3c+4nJnCG81mwHINtEH/cDkt0E6RbB7H1qynykpKINfr6xv4FLGLIHDrzAT409uUku3PxyMRGfjU8RF/Te6PQp7oybIEfpdq0enGJB0GLBlmqd/FGIKUkxmCB1/3glLuOpJA/vtM1sSAtLT+2U3a/C+nIwLEmLCw8mmuFWL+RrIeh13bBP0tKmdewNZagMCMU7KCl3Eq1AVjuIbdCK5twKsDy0WHt4BgozUu/X9dfmfexkhYCO1AuYFd5mOjQCIs2qpppNKN1JWgEeFdUOdDAvPncI+NNP4JvPz3Y/AKcz/H/SiZ2ROHhNgzoI/9lHnENLz1nsgB8SDJgBDXbaiLOmoo6KkBx4WzHwxB2gDJntvElE8ErfzqQpmMFkE66xlOO+822xUEhVQMFni9M5AzYQaPSwGMEHQPzdkR8vUtChmqg5CEXTYn+4tezkT","X-OriginatorOrg":"Nvidia.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"16 Apr 2026 23:30:09.4579\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 7f18b5f4-6b3c-493e-4433-08de9c10198a","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tCO1PEPF00012E80.namprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"BL1PR12MB5996"},"content":"The flag will be set when IOMMU cannot trust device's ATS function. E.g.,\nwhen ATC invalidation request to the device times out.\n\nOnce it is set, unsupport the ATS feature to prevent data corruption, and\nskip further ATC invalidation commands to avoid new timeouts.\n\nUnset the flag when the device finishes a reset for recovery.\n\nSigned-off-by: Nicolin Chen \n---\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 +\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 28 +++++++++++++++++++++\n 2 files changed, 29 insertions(+)","diff":"diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\nindex 26e0ee0bb5b45..95bce9966374a 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n@@ -941,6 +941,7 @@ struct arm_smmu_master {\n \t/* Locked by the iommu core using the group mutex */\n \tstruct arm_smmu_ctx_desc_cfg\tcd_table;\n \tunsigned int\t\t\tnum_streams;\n+\tbool\t\t\t\tats_broken;\n \tbool\t\t\t\tats_enabled : 1;\n \tbool\t\t\t\tste_ats_enabled : 1;\n \tbool\t\t\t\tstall_enabled;\ndiff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\nindex 13f225f704e73..5dead82cf1186 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n@@ -2523,6 +2523,10 @@ static int arm_smmu_atc_inv_master(struct arm_smmu_master *master,\n \tstruct arm_smmu_cmdq_ent cmd;\n \tstruct arm_smmu_cmdq_batch cmds;\n \n+\t/* Do not issue ATC_INV that will definitely time out */\n+\tif (READ_ONCE(master->ats_broken))\n+\t\treturn 0;\n+\n \tarm_smmu_atc_inv_to_cmd(ssid, 0, 0, &cmd);\n \n \tarm_smmu_cmdq_batch_init(master->smmu, &cmds, &cmd);\n@@ -2729,11 +2733,17 @@ static void __arm_smmu_domain_inv_range(struct arm_smmu_invs *invs,\n \t\t\tarm_smmu_cmdq_batch_add(smmu, &cmds, &cmd);\n \t\t\tbreak;\n \t\tcase INV_TYPE_ATS:\n+\t\t\t/* Do not issue ATC_INV that will definitely time out */\n+\t\t\tif (READ_ONCE(cur->master->ats_broken))\n+\t\t\t\tbreak;\n \t\t\tarm_smmu_atc_inv_to_cmd(cur->ssid, iova, size, &cmd);\n \t\t\tcmd.atc.sid = cur->id;\n \t\t\tarm_smmu_cmdq_batch_add(smmu, &cmds, &cmd);\n \t\t\tbreak;\n \t\tcase INV_TYPE_ATS_FULL:\n+\t\t\t/* Do not issue ATC_INV that will definitely time out */\n+\t\t\tif (READ_ONCE(cur->master->ats_broken))\n+\t\t\t\tbreak;\n \t\t\tarm_smmu_atc_inv_to_cmd(IOMMU_NO_PASID, 0, 0, &cmd);\n \t\t\tcmd.atc.sid = cur->id;\n \t\t\tarm_smmu_cmdq_batch_add(smmu, &cmds, &cmd);\n@@ -3069,6 +3079,15 @@ void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master,\n \t}\n }\n \n+static void arm_smmu_reset_device_done(struct device *dev)\n+{\n+\tstruct arm_smmu_master *master = dev_iommu_priv_get(dev);\n+\n+\tif (WARN_ON(!master))\n+\t\treturn;\n+\tWRITE_ONCE(master->ats_broken, false);\n+}\n+\n static bool arm_smmu_ats_supported(struct arm_smmu_master *master)\n {\n \tstruct device *dev = master->dev;\n@@ -3081,6 +3100,14 @@ static bool arm_smmu_ats_supported(struct arm_smmu_master *master)\n \tif (!(fwspec->flags & IOMMU_FWSPEC_PCI_RC_ATS))\n \t\treturn false;\n \n+\t/*\n+\t * Do not enable ATS if master->ats_broken is set. The PCI device should\n+\t * go through a recovery (reset) that shall notify the SMMUv3 driver via\n+\t * a reset_device_done callback.\n+\t */\n+\tif (READ_ONCE(master->ats_broken))\n+\t\treturn false;\n+\n \treturn dev_is_pci(dev) && pci_ats_supported(to_pci_dev(dev));\n }\n \n@@ -4412,6 +4439,7 @@ static const struct iommu_ops arm_smmu_ops = {\n \t.domain_alloc_paging_flags = arm_smmu_domain_alloc_paging_flags,\n \t.probe_device\t\t= arm_smmu_probe_device,\n \t.release_device\t\t= arm_smmu_release_device,\n+\t.reset_device_done\t= arm_smmu_reset_device_done,\n \t.device_group\t\t= arm_smmu_device_group,\n \t.of_xlate\t\t= arm_smmu_of_xlate,\n \t.get_resv_regions\t= arm_smmu_get_resv_regions,\n","prefixes":["v3","10/11"]}