{"id":2224144,"url":"http://patchwork.ozlabs.org/api/patches/2224144/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/bf99f11ac9a42b5552ec3367d02840366459ae7b.1776381841.git.nicolinc@nvidia.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-04-16T23:28:31","name":"[v3,02/11] iommu: Pass in reset result to pci_dev_reset_iommu_done()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"46f3bcb67c10be231b67dfbe154bb9d0fdf620bb","submitter":{"id":82183,"url":"http://patchwork.ozlabs.org/api/people/82183/?format=json","name":"Nicolin Chen","email":"nicolinc@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/bf99f11ac9a42b5552ec3367d02840366459ae7b.1776381841.git.nicolinc@nvidia.com/mbox/","series":[{"id":500217,"url":"http://patchwork.ozlabs.org/api/series/500217/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=500217","date":"2026-04-16T23:28:31","name":"iommu/arm-smmu-v3: Quarantine device upon ATC invalidation timeout","version":3,"mbox":"http://patchwork.ozlabs.org/series/500217/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224144/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224144/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=bzq+DuGj;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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Wysocki\" , Len Brown ,\n\tPranjal Shrivastava , Mostafa Saleh ,\n\tLu Baolu , Kevin Tian ,\n\t, ,\n\t, ,\n\t, , Shuai Xue\n\t","Subject":"[PATCH v3 02/11] iommu: Pass in reset result to\n pci_dev_reset_iommu_done()","Date":"Thu, 16 Apr 2026 16:28:31 -0700","Message-ID":"\n ","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"","References":"","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-NV-OnPremToCloud":"ExternallySecured","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"SJ1PEPF00002312:EE_|MN0PR12MB6271:EE_","X-MS-Office365-Filtering-Correlation-Id":"a43b944e-5240-4b3f-12f4-08de9c0ff7ce","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"\n\tBCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|7416014|18096099003|18002099003|22082099003|56012099003;","X-Microsoft-Antispam-Message-Info":"\n\tpg8GX5yXs5RDNmAfNcGG35xj0pvGHBQwfgSNTMdlShThl15IQpQaxI4i0JVqqvp2bsoR3X1bTpGwWVr/3ArLefKk3CnNHN6GxbcyDq34uGgDe2IpjYj8q0jMLBou9BY7ThA2qcbdkSknhPAJgts45O0u20Goq9zHJNDD365N8vJ+7wfppo0u/pz0V8Dtb9LeX2TSwSx2u2BgW+ppcF2pbVByJX3/j7lO0zKXmQcP7+mR/LRftqC1iefqu9cfxekLcW18QE41JxVn4zWaOtZYCx85xvJZNL77j+vWGc6YmdKnACQviaqrCHba11NqIfan5G2/9hoHeH1U14HERhdLRYt2pxuK/9EXrvjnuE4J5g8jFX+YHP1lbUsJnZZU4rg1w0AlWOxHBsaTT0JB9M+Zk4gpTs7VJ69YondT4cKewqgH5FzghheLBm2xV3vy1OgtxwqkOYcswJ5qxrU4QIKYQEnYA2nJp1hRWZLbMmqY5elLwuRH8nFmuqLtJMf8ksmYDE/xW/DKydeTh9OSq8TUhgoA98rSWDcL8AVm+tIhEgpGoXZlMwi0cUMCPwBWJoOAcBx9wkW8tid8vx3P+XWvT4dHGnA7LGDNF8RT24GHfRGXftJNFgYKAB+hqqDASt0X3CELKwbGNgNw69JbxBxGdj0raK/NZ1Rs4w8Qq8Fv1e7Tub321dzp1TLtidLRlPwi/1sWvTkSXs0OyCWVBHdJex8oeYlsfOU2diiP30/CXCpDJJMl4lbNzJW2tTnha3CZ0WQgvqgEBMI52Mci/9xGpg==","X-Forefront-Antispam-Report":"\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(7416014)(18096099003)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101;","X-MS-Exchange-AntiSpam-MessageData-ChunkCount":"1","X-MS-Exchange-AntiSpam-MessageData-0":"\n\tmajVbgy+FACEw0Ap6Xo48gWE7+6Evo7ycUNdAEMbeWpt/tj/RMsEvbJ2iUyiqUPHSApWVsR8eDjaJuLkqbfOdMF3D0Xa7XHTZcYx6GyA331e+7vTzdcYH1+ZQu1OodUs7iJvJUeJ715CKcQbOX+KnEfWgzkp9msNNisao2nsxr2qhAvIHTj3cHcd4Wsmy3nnzyBCt7VTRF9GYU6eCeutAroMbKrUgIdHeTRfVX9unqqYgBdvW7MTffA5RFRRgPqE2oGGP6HpgRLJu0IM7lgIiJ834NscDUREQd+23wlOAzsjZ9sy4WtI1LPw8tZ6s6nC0Nj0vkMy9yPte0I+ZB3l1imfV5d7dLDHOmSu1jiRR1AgAZE8bx/xBexxEX4luKbKIakyjIeb97PjN2/xRYU2l2rwe4YCalOAMIS9UeWZZLn28LOSgWKPMywdAyl2sxmc","X-OriginatorOrg":"Nvidia.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"16 Apr 2026 23:29:12.7761\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n a43b944e-5240-4b3f-12f4-08de9c0ff7ce","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tSJ1PEPF00002312.namprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"MN0PR12MB6271"},"content":"IOMMU drivers handle ATC cache maintenance. They may encounter ATC-related\nerrors (e.g., ATC invalidation request timeout), indicating that ATC cache\nmight have stale entries that can corrupt the memory. In this case, IOMMU\ndriver has no choice but to block the device's ATS function and wait for a\ndevice recovery.\n\nThe pci_dev_reset_iommu_done() called at the end of a reset function could\nserve as a reliable signal to the IOMMU subsystem that the physical device\ncache is completely clean. However, the function is called unconditionally\neven if the reset operation had actually failed, which would re-attach the\nfaulty device back to a normal translation domain. And this will leave the\nsystem highly exposed, creating vulnerabilities for data corruption:\n IOMMU blocks RID/ATS\n pci_reset_function():\n pci_dev_reset_iommu_prepare(); // Block RID/ATS\n __reset(); // Failed (ATC is still stale)\n pci_dev_reset_iommu_done(); // Unblock RID/ATS (ah-ha)\n\nInstead, add a @reset_succeeds parameter to pci_dev_reset_iommu_done() and\npass the reset result from each caller:\n IOMMU blocks RID/ATS\n pci_reset_function():\n pci_dev_reset_iommu_prepare(); // Block RID/ATS\n rc = __reset();\n pci_dev_reset_iommu_done(!rc); // Unblock or quarantine\n\nOn a successful reset, done() restores the device to its RID/PASID domains\nand decrements group->recovery_cnt. On failure, the device remains blocked,\nand concurrent domain attachment will be rejected until a successful reset.\n\nSuggested-by: Kevin Tian \nSigned-off-by: Nicolin Chen \n---\n include/linux/iommu.h | 5 +++--\n drivers/iommu/iommu.c | 28 +++++++++++++++++++++++++---\n drivers/pci/pci-acpi.c | 2 +-\n drivers/pci/pci.c | 10 +++++-----\n drivers/pci/quirks.c | 2 +-\n 5 files changed, 35 insertions(+), 12 deletions(-)","diff":"diff --git a/include/linux/iommu.h b/include/linux/iommu.h\nindex 54b8b48c762e8..d3685967e960a 100644\n--- a/include/linux/iommu.h\n+++ b/include/linux/iommu.h\n@@ -1191,7 +1191,7 @@ void iommu_free_global_pasid(ioasid_t pasid);\n \n /* PCI device reset functions */\n int pci_dev_reset_iommu_prepare(struct pci_dev *pdev);\n-void pci_dev_reset_iommu_done(struct pci_dev *pdev);\n+void pci_dev_reset_iommu_done(struct pci_dev *pdev, bool reset_succeeds);\n #else /* CONFIG_IOMMU_API */\n \n struct iommu_ops {};\n@@ -1521,7 +1521,8 @@ static inline int pci_dev_reset_iommu_prepare(struct pci_dev *pdev)\n \treturn 0;\n }\n \n-static inline void pci_dev_reset_iommu_done(struct pci_dev *pdev)\n+static inline void pci_dev_reset_iommu_done(struct pci_dev *pdev,\n+\t\t\t\t\t bool reset_succeeds)\n {\n }\n #endif /* CONFIG_IOMMU_API */\ndiff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c\nindex ff181db687bbf..28d4c1f143a08 100644\n--- a/drivers/iommu/iommu.c\n+++ b/drivers/iommu/iommu.c\n@@ -80,6 +80,7 @@ struct group_device {\n \t * Device is blocked for a pending recovery while its group->domain is\n \t * retained. This can happen when:\n \t * - Device is undergoing a reset\n+\t * - Device failed the last reset\n \t */\n \tbool blocked;\n \tunsigned int reset_depth;\n@@ -3971,7 +3972,9 @@ EXPORT_SYMBOL_NS_GPL(iommu_replace_group_handle, \"IOMMUFD_INTERNAL\");\n * reset is finished, pci_dev_reset_iommu_done() can restore everything.\n *\n * Caller must use pci_dev_reset_iommu_prepare() with pci_dev_reset_iommu_done()\n- * before/after the core-level reset routine, to decrement the recovery_cnt.\n+ * before/after the core-level reset routine. On a successful reset, done() will\n+ * decrement group->recovery_cnt and restore domains. On a failure, recovery_cnt\n+ * is left intact and the device stays blocked.\n *\n * Return: 0 on success or negative error code if the preparation failed.\n *\n@@ -4000,6 +4003,9 @@ int pci_dev_reset_iommu_prepare(struct pci_dev *pdev)\n \n \tif (gdev->reset_depth++)\n \t\treturn 0;\n+\t/* Device might be already blocked for a quarantine */\n+\tif (gdev->blocked)\n+\t\treturn 0;\n \n \tret = __iommu_group_alloc_blocking_domain(group);\n \tif (ret)\n@@ -4047,18 +4053,22 @@ EXPORT_SYMBOL_GPL(pci_dev_reset_iommu_prepare);\n /**\n * pci_dev_reset_iommu_done() - Restore IOMMU after a PCI device reset is done\n * @pdev: PCI device that has finished a reset routine\n+ * @reset_succeeds: Whether the PCI device reset is successful or not\n *\n * After a PCIe device finishes a reset routine, it wants to restore its IOMMU\n * activity, including new translation and cache invalidation, by re-attaching\n * all RID/PASID of the device back to the domains retained in the core-level\n * structure.\n *\n- * Caller must pair it with a successful pci_dev_reset_iommu_prepare().\n+ * This is a pairing function for pci_dev_reset_iommu_prepare(). Caller should\n+ * pass in the reset state via @reset_succeeds. On a failed reset, the device\n+ * remains blocked for a quarantine with the group->recovery_cnt intact, so as\n+ * to protect system memory until a subsequent successful reset.\n *\n * Note that, although unlikely, there is a risk that re-attaching domains might\n * fail due to some unexpected happening like OOM.\n */\n-void pci_dev_reset_iommu_done(struct pci_dev *pdev)\n+void pci_dev_reset_iommu_done(struct pci_dev *pdev, bool reset_succeeds)\n {\n \tstruct iommu_group *group = pdev->dev.iommu_group;\n \tstruct group_device *gdev;\n@@ -4083,6 +4093,18 @@ void pci_dev_reset_iommu_done(struct pci_dev *pdev)\n \tif (WARN_ON(!group->blocking_domain))\n \t\treturn;\n \n+\t/*\n+\t * A reset failure implies that the device might be unreliable. E.g. its\n+\t * device cache might retain stale entries, which potentially results in\n+\t * memory corruption. Thus, do not unblock the device until a successful\n+\t * reset.\n+\t */\n+\tif (!reset_succeeds) {\n+\t\tpci_err(pdev,\n+\t\t\t\"Reset failed. Keep it blocked to protect memory\\n\");\n+\t\treturn;\n+\t}\n+\n \t/* Re-attach RID domain back to group->domain */\n \tif (group->domain != group->blocking_domain) {\n \t\tWARN_ON(__iommu_attach_device(group->domain, &pdev->dev,\ndiff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c\nindex 4d0f2cb6c695b..9ffd7f013a7d4 100644\n--- a/drivers/pci/pci-acpi.c\n+++ b/drivers/pci/pci-acpi.c\n@@ -977,7 +977,7 @@ int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)\n \t\tret = -ENOTTY;\n \t}\n \n-\tpci_dev_reset_iommu_done(dev);\n+\tpci_dev_reset_iommu_done(dev, !ret);\n \treturn ret;\n }\n \ndiff --git a/drivers/pci/pci.c b/drivers/pci/pci.c\nindex 8479c2e1f74f1..d78e724027c78 100644\n--- a/drivers/pci/pci.c\n+++ b/drivers/pci/pci.c\n@@ -4358,7 +4358,7 @@ int pcie_flr(struct pci_dev *dev)\n \n \tret = pci_dev_wait(dev, \"FLR\", PCIE_RESET_READY_POLL_MS);\n done:\n-\tpci_dev_reset_iommu_done(dev);\n+\tpci_dev_reset_iommu_done(dev, !ret);\n \treturn ret;\n }\n EXPORT_SYMBOL_GPL(pcie_flr);\n@@ -4436,7 +4436,7 @@ static int pci_af_flr(struct pci_dev *dev, bool probe)\n \n \tret = pci_dev_wait(dev, \"AF_FLR\", PCIE_RESET_READY_POLL_MS);\n done:\n-\tpci_dev_reset_iommu_done(dev);\n+\tpci_dev_reset_iommu_done(dev, !ret);\n \treturn ret;\n }\n \n@@ -4490,7 +4490,7 @@ static int pci_pm_reset(struct pci_dev *dev, bool probe)\n \tpci_dev_d3_sleep(dev);\n \n \tret = pci_dev_wait(dev, \"PM D3hot->D0\", PCIE_RESET_READY_POLL_MS);\n-\tpci_dev_reset_iommu_done(dev);\n+\tpci_dev_reset_iommu_done(dev, !ret);\n \treturn ret;\n }\n \n@@ -4933,7 +4933,7 @@ static int pci_reset_bus_function(struct pci_dev *dev, bool probe)\n \n \trc = pci_parent_bus_reset(dev, probe);\n done:\n-\tpci_dev_reset_iommu_done(dev);\n+\tpci_dev_reset_iommu_done(dev, !rc);\n \treturn rc;\n }\n \n@@ -4978,7 +4978,7 @@ static int cxl_reset_bus_function(struct pci_dev *dev, bool probe)\n \t\tpci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL,\n \t\t\t\t reg);\n \n-\tpci_dev_reset_iommu_done(dev);\n+\tpci_dev_reset_iommu_done(dev, !rc);\n \treturn rc;\n }\n \ndiff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\nindex 05ce12b6b2f76..6ce79a25e5c76 100644\n--- a/drivers/pci/quirks.c\n+++ b/drivers/pci/quirks.c\n@@ -4271,7 +4271,7 @@ static int __pci_dev_specific_reset(struct pci_dev *dev, bool probe,\n \t}\n \n \tret = i->reset(dev, probe);\n-\tpci_dev_reset_iommu_done(dev);\n+\tpci_dev_reset_iommu_done(dev, !ret);\n \treturn ret;\n }\n \n","prefixes":["v3","02/11"]}