{"id":2224122,"url":"http://patchwork.ozlabs.org/api/patches/2224122/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260416210508.30686-2-philmd@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260416210508.30686-2-philmd@linaro.org>","list_archive_url":null,"date":"2026-04-16T21:05:05","name":"[v4,1/4] target/mips: Pass MemOpIdx argument to Load/Store Multiple helpers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f10be251d275df1f9b805a8a38865dc5c2b539e8","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260416210508.30686-2-philmd@linaro.org/mbox/","series":[{"id":500206,"url":"http://patchwork.ozlabs.org/api/series/500206/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500206","date":"2026-04-16T21:05:04","name":"target/mips: Replace cpu_ld/st_mmuidx_ra() calls in LD/ST Multiple","version":4,"mbox":"http://patchwork.ozlabs.org/series/500206/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224122/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224122/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=czbAiUMH;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32f;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"In preparation of using the MemOp content in the next commit,\npass it as MemOpIdx. Include the access size.\n\nSigned-off-by: Philippe Mathieu-Daudé \n---\n target/mips/tcg/ldst_helper.c | 16 ++++++++++++----\n target/mips/tcg/micromips_translate.c.inc | 16 ++++++++++------\n 2 files changed, 22 insertions(+), 10 deletions(-)","diff":"diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c\nindex 4ebf72d610e..7be2cad89d6 100644\n--- a/target/mips/tcg/ldst_helper.c\n+++ b/target/mips/tcg/ldst_helper.c\n@@ -224,8 +224,10 @@ void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,\n static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };\n \n void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,\n- uint32_t mem_idx)\n+ uint32_t memop_idx)\n {\n+ MemOpIdx oi = memop_idx;\n+ unsigned mem_idx = get_mmuidx(oi);\n target_ulong base_reglist = reglist & 0xf;\n target_ulong do_r31 = reglist & 0x10;\n \n@@ -246,8 +248,10 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,\n }\n \n void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,\n- uint32_t mem_idx)\n+ uint32_t memop_idx)\n {\n+ MemOpIdx oi = memop_idx;\n+ unsigned mem_idx = get_mmuidx(oi);\n target_ulong base_reglist = reglist & 0xf;\n target_ulong do_r31 = reglist & 0x10;\n \n@@ -268,8 +272,10 @@ void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,\n \n #if defined(TARGET_MIPS64)\n void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,\n- uint32_t mem_idx)\n+ uint32_t memop_idx)\n {\n+ MemOpIdx oi = memop_idx;\n+ unsigned mem_idx = get_mmuidx(oi);\n target_ulong base_reglist = reglist & 0xf;\n target_ulong do_r31 = reglist & 0x10;\n \n@@ -290,8 +296,10 @@ void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,\n }\n \n void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,\n- uint32_t mem_idx)\n+ uint32_t memop_idx)\n {\n+ MemOpIdx oi = memop_idx;\n+ unsigned mem_idx = get_mmuidx(oi);\n target_ulong base_reglist = reglist & 0xf;\n target_ulong do_r31 = reglist & 0x10;\n \ndiff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc\nindex 8fda7c8a214..4dca11b84b4 100644\n--- a/target/mips/tcg/micromips_translate.c.inc\n+++ b/target/mips/tcg/micromips_translate.c.inc\n@@ -693,7 +693,8 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,\n int base, int16_t offset)\n {\n TCGv t0, t1;\n- TCGv_i32 t2;\n+ MemOp mop = MO_UNALN;\n+ MemOpIdx oi;\n \n if (ctx->hflags & MIPS_HFLAG_BMASK) {\n gen_reserved_instruction(ctx);\n@@ -705,22 +706,25 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,\n gen_base_offset_addr(ctx, t0, base, offset);\n \n t1 = tcg_constant_tl(reglist);\n- t2 = tcg_constant_i32(ctx->mem_idx);\n \n save_cpu_state(ctx, 1);\n switch (opc) {\n case LWM32:\n- gen_helper_lwm(tcg_env, t0, t1, t2);\n+ oi = make_memop_idx(mop | MO_UL, ctx->mem_idx);\n+ gen_helper_lwm(tcg_env, t0, t1, tcg_constant_i32(oi));\n break;\n case SWM32:\n- gen_helper_swm(tcg_env, t0, t1, t2);\n+ oi = make_memop_idx(mop | MO_UL, ctx->mem_idx);\n+ gen_helper_swm(tcg_env, t0, t1, tcg_constant_i32(oi));\n break;\n #ifdef TARGET_MIPS64\n case LDM:\n- gen_helper_ldm(tcg_env, t0, t1, t2);\n+ oi = make_memop_idx(mop | MO_UQ, ctx->mem_idx);\n+ gen_helper_ldm(tcg_env, t0, t1, tcg_constant_i32(oi));\n break;\n case SDM:\n- gen_helper_sdm(tcg_env, t0, t1, t2);\n+ oi = make_memop_idx(mop | MO_UQ, ctx->mem_idx);\n+ gen_helper_sdm(tcg_env, t0, t1, tcg_constant_i32(oi));\n break;\n #endif\n }\n","prefixes":["v4","1/4"]}