{"id":2224005,"url":"http://patchwork.ozlabs.org/api/patches/2224005/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20260416141309.584051-1-rearnsha@arm.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260416141309.584051-1-rearnsha@arm.com>","list_archive_url":null,"date":"2026-04-16T14:13:09","name":"[committed] arm: support +CDECP options on cortex-m85","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"41e96a759a692777edb5895714789a6b730ec39a","submitter":{"id":4378,"url":"http://patchwork.ozlabs.org/api/people/4378/?format=json","name":"Richard Earnshaw","email":"rearnsha@arm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20260416141309.584051-1-rearnsha@arm.com/mbox/","series":[{"id":500169,"url":"http://patchwork.ozlabs.org/api/series/500169/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=500169","date":"2026-04-16T14:13:09","name":"[committed] arm: support +CDECP options on cortex-m85","version":1,"mbox":"http://patchwork.ozlabs.org/series/500169/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2224005/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2224005/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=foss header.b=Imk5btij;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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a=rsa-sha256; d=sourceware.org; s=key;\n t=1776348802; c=relaxed/simple;\n bh=2iJxkdyHFJoyuq9lNaYoX34Fb0Y7cdgvfjQk/l8tOlw=;\n h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version;\n b=I2Q9ACA/gCd9XRnkLXH39yy7XjStls8F9BlelcbiE5BjwB21JPwvMRgO9JqpodJOv/TgYJ/YceNu5pKYr5A7fW5MB1qbpzB/4Al7S2L87P8JuuwwpPnUDu3RVWHaNpUBQrjoohT/t/bquZmP3m1jnPgG//qogowRqRdIrLy9AhU=","ARC-Authentication-Results":"i=1; server2.sourceware.org","DKIM-Signature":"v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss;\n t=1776348800; bh=2iJxkdyHFJoyuq9lNaYoX34Fb0Y7cdgvfjQk/l8tOlw=;\n h=From:To:Cc:Subject:Date:From;\n b=Imk5btijZ+kCRX33poTrOfrc9tLz4VoAFfeLA3OoDUT/a1rRz7ixvqdpIjjY00C8W\n BJIv/2/+KS1DuM88oEtgVY2CYfXp/iTX6RpwBU/AS1nPhXuDgzMZVtLtEwHpZxzVbd\n A6OpiN+dClihsliqY2VAuNXR4K1OP41zFm4qTBw0=","From":"Richard Earnshaw ","To":"gcc-patches@gcc.gnu.org","Cc":"Richard Earnshaw ","Subject":"[committed] arm: support +CDECP options on cortex-m85","Date":"Thu, 16 Apr 2026 15:13:09 +0100","Message-ID":"<20260416141309.584051-1-rearnsha@arm.com>","X-Mailer":"git-send-email 2.43.0","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"The Cortex-m85 CPU supports the CDE extension, which requires use of the\n+cdecp CPU name modifiers. This patch enables these options. This is\nall pretty-much boiler-plate since Srinath added support on Cortex-m55.\n\ngcc/ChangeLog:\n\n\t* config/arm/arm-cpus.in (cortex-m85): Allow +cdecp.\n\t* doc/invoke.texi: Document this\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/arm/multilib.exp: Test CDE options on cortex-m85.\n---\n gcc/config/arm/arm-cpus.in | 8 ++++++++\n gcc/doc/invoke.texi | 2 +-\n gcc/testsuite/gcc.target/arm/multilib.exp | 11 +++++++++++\n 3 files changed, 20 insertions(+), 1 deletion(-)","diff":"diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in\nindex f66870a303d..db674b85af1 100644\n--- a/gcc/config/arm/arm-cpus.in\n+++ b/gcc/config/arm/arm-cpus.in\n@@ -1694,6 +1694,14 @@ begin cpu cortex-m85\n option nomve remove mve mve_float\n option nofp remove ALL_FP mve_float\n option nodsp remove MVE mve_float\n+ option cdecp0 add cdecp0\n+ option cdecp1 add cdecp1\n+ option cdecp2 add cdecp2\n+ option cdecp3 add cdecp3\n+ option cdecp4 add cdecp4\n+ option cdecp5 add cdecp5\n+ option cdecp6 add cdecp6\n+ option cdecp7 add cdecp7\n isa quirk_no_asmcpu quirk_vlldm\n costs v7m\n part 0xd23\ndiff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi\nindex a3ac487eeaa..dc83623d48b 100644\n--- a/gcc/doc/invoke.texi\n+++ b/gcc/doc/invoke.texi\n@@ -23683,7 +23683,7 @@ instructions on @samp{cortex-m52}, @samp{cortex-m55} and @samp{cortex-m85}.\n @item +cdecp0, +cdecp1, ... , +cdecp7\n Enable the Custom Datapath Extension (CDE) on selected coprocessors according\n to the numbers given in the options in the range 0 to 7 on @samp{cortex-m52},\n-@samp{cortex-m55} and @samp{star-mc1}.\n+@samp{cortex-m55}, @samp{cortex-m85} and @samp{star-mc1}.\n \n @item +nofp\n Disables the floating-point instructions on @samp{arm9e},\ndiff --git a/gcc/testsuite/gcc.target/arm/multilib.exp b/gcc/testsuite/gcc.target/arm/multilib.exp\nindex b824173e798..29376c49df8 100644\n--- a/gcc/testsuite/gcc.target/arm/multilib.exp\n+++ b/gcc/testsuite/gcc.target/arm/multilib.exp\n@@ -526,6 +526,7 @@ if {[multilib_config \"rmprofile\"] } {\n \t{-mcpu=cortex-m23 -mfpu=fpv5-d16 -mfloat-abi=soft} \"thumb/v8-m.base/nofp\"\n \t{-mcpu=cortex-m33 -mfpu=fpv5-d16 -mfloat-abi=soft} \"thumb/v8-m.main/nofp\"\n \t{-mcpu=cortex-m7+nofp.dp -mfpu=fpv5-d16 -mfloat-abi=soft} \"thumb/v7e-m/nofp\"\n+\n \t{-mcpu=cortex-m85+nopacbti -mfpu=auto -mfloat-abi=soft} \"thumb/v8-m.main/nofp\"\n \t{-mcpu=cortex-m85+nopacbti+nofp -mfpu=auto -mfloat-abi=soft} \"thumb/v8-m.main/nofp\"\n \t{-mcpu=cortex-m85+nopacbti+nomve -mfpu=auto -mfloat-abi=soft} \"thumb/v8-m.main/nofp\"\n@@ -535,6 +536,16 @@ if {[multilib_config \"rmprofile\"] } {\n \t{-mcpu=cortex-m85+nomve.fp -mfpu=auto -mfloat-abi=soft} \"thumb/v8-m.main/nofp\"\n \t{-mcpu=cortex-m85+nomve -mfpu=auto -mfloat-abi=soft} \"thumb/v8-m.main/nofp\"\n \t{-mcpu=cortex-m85+nodsp -mfpu=auto -mfloat-abi=soft} \"thumb/v8-m.main/nofp\"\n+\t{-mcpu=cortex-m85+nopacbti+cdecp0 -mfpu=auto -mfloat-abi=soft} \"thumb/v8-m.main/nofp\"\n+\t{-mcpu=cortex-m85+nopacbti+cdecp1+nofp -mfpu=auto -mfloat-abi=soft} \"thumb/v8-m.main/nofp\"\n+\t{-mcpu=cortex-m85+nopacbti+cdecp7+nomve -mfpu=auto -mfloat-abi=soft} \"thumb/v8-m.main/nofp\"\n+\t{-mcpu=cortex-m85+nopacbti+cdecp0+cdecp1+nodsp -mfpu=auto -mfloat-abi=soft} \"thumb/v8-m.main/nofp\"\n+\t{-mcpu=cortex-m85+nopacbti+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7+nomve.fp -mfpu=auto -mfloat-abi=soft} \"thumb/v8-m.main/nofp\"\n+\t{-mcpu=cortex-m85+cdecp6 -mfpu=auto -mfloat-abi=soft} \"thumb/v8-m.main/nofp\"\n+\t{-mcpu=cortex-m85+cdecp4+nomve.fp -mfpu=auto -mfloat-abi=soft} \"thumb/v8-m.main/nofp\"\n+\t{-mcpu=cortex-m85+cdecp5+nomve -mfpu=auto -mfloat-abi=soft} \"thumb/v8-m.main/nofp\"\n+\t{-mcpu=cortex-m85+cdecp2+nodsp -mfpu=auto -mfloat-abi=soft} \"thumb/v8-m.main/nofp\"\n+\n \t{-mcpu=cortex-m4 -mfpu=auto -mfloat-abi=hard} \"thumb/v7e-m+fp/hard\"\n \t{-mcpu=cortex-m7 -mfpu=auto -mfloat-abi=hard} \"thumb/v7e-m+dp/hard\"\n \t{-mcpu=cortex-m33 -mfpu=auto -mfloat-abi=hard} \"thumb/v8-m.main+fp/hard\"\n","prefixes":["committed"]}