{"id":2223925,"url":"http://patchwork.ozlabs.org/api/patches/2223925/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/96e27588ad5a7d47ba9f56f1d547729a19b691c5.1776339451.git.matheus.bernardino@oss.qualcomm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<96e27588ad5a7d47ba9f56f1d547729a19b691c5.1776339451.git.matheus.bernardino@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-16T11:38:59","name":"[v5,10/16] target/hexagon: add v68 HVX IEEE float compare insns","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0be1bf4b8f09bcd451a21697d6c2dbe6e76cfd7b","submitter":{"id":90606,"url":"http://patchwork.ozlabs.org/api/people/90606/?format=json","name":"Matheus Tavares Bernardino","email":"matheus.bernardino@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/96e27588ad5a7d47ba9f56f1d547729a19b691c5.1776339451.git.matheus.bernardino@oss.qualcomm.com/mbox/","series":[{"id":500137,"url":"http://patchwork.ozlabs.org/api/series/500137/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500137","date":"2026-04-16T11:38:50","name":"hexagon: add missing HVX float instructions","version":5,"mbox":"http://patchwork.ozlabs.org/series/500137/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223925/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223925/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=BkpuZxFR;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=eNaN/+C1;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n 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","To":"qemu-devel@nongnu.org","Cc":"richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com","Subject":"[PATCH v5 10/16] target/hexagon: add v68 HVX IEEE float compare insns","Date":"Thu, 16 Apr 2026 04:38:59 -0700","Message-Id":"\n <96e27588ad5a7d47ba9f56f1d547729a19b691c5.1776339451.git.matheus.bernardino@oss.qualcomm.com>","X-Mailer":"git-send-email 2.37.2","In-Reply-To":"","References":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-ORIG-GUID":"jNu58ZhU7SuXSwTeKwN0X2a4KxrYqz_y","X-Proofpoint-GUID":"jNu58ZhU7SuXSwTeKwN0X2a4KxrYqz_y","X-Authority-Analysis":"v=2.4 cv=XOIAjwhE c=1 sm=1 tr=0 ts=69e0ca68 cx=c_pps\n a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 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","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add HVX IEEE floating-point compare instructions:\n- V6_vgthf, V6_vgtsf: greater-than compare\n- V6_vgthf_and, V6_vgtsf_and: greater-than with predicate-and\n- V6_vgthf_or, V6_vgtsf_or: greater-than with predicate-or\n- V6_vgthf_xor, V6_vgtsf_xor: greater-than with predicate-xor\n\nReviewed-by: Taylor Simpson \nSigned-off-by: Matheus Tavares Bernardino \n---\n target/hexagon/mmvec/hvx_ieee_fp.h | 4 ++\n target/hexagon/mmvec/macros.h | 3 +\n target/hexagon/mmvec/hvx_ieee_fp.c | 48 +++++++++++++++\n target/hexagon/imported/mmvec/encode_ext.def | 10 ++++\n target/hexagon/imported/mmvec/ext.idef | 61 ++++++++++++++++++++\n 5 files changed, 126 insertions(+)","diff":"diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_ieee_fp.h\nindex bdc21e08f0..01728121eb 100644\n--- a/target/hexagon/mmvec/hvx_ieee_fp.h\n+++ b/target/hexagon/mmvec/hvx_ieee_fp.h\n@@ -25,4 +25,8 @@ float16 qf_min_hf(float16 a1, float16 a2, float_status *fp_status);\n int32_t conv_w_sf(float32 a, float_status *fp_status);\n int16_t conv_h_hf(float16 a, float_status *fp_status);\n \n+/* IEEE - FP compare instructions */\n+uint32_t cmpgt_sf(float32 a1, float32 a2, float_status *fp_status);\n+uint16_t cmpgt_hf(float16 a1, float16 a2, float_status *fp_status);\n+\n #endif\ndiff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h\nindex ac709d8993..318d44efb7 100644\n--- a/target/hexagon/mmvec/macros.h\n+++ b/target/hexagon/mmvec/macros.h\n@@ -356,4 +356,7 @@\n extract32(VAL, POS * 8, 8); \\\n } while (0);\n \n+#define fCMPGT_SF(A, B) cmpgt_sf(A, B, &env->hvx_fp_status)\n+#define fCMPGT_HF(A, B) cmpgt_hf(A, B, &env->hvx_fp_status)\n+\n #endif\ndiff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_ieee_fp.c\nindex 697f35b5ed..d7751adbe2 100644\n--- a/target/hexagon/mmvec/hvx_ieee_fp.c\n+++ b/target/hexagon/mmvec/hvx_ieee_fp.c\n@@ -87,3 +87,51 @@ int16_t conv_h_hf(float16 a, float_status *fp_status)\n }\n return float16_to_int16_round_to_zero(a, fp_status);\n }\n+\n+/*\n+ * Returns true if f1 > f2, where at least one of the elements is guaranteed\n+ * to be NaN.\n+ * Up to v73, Hexagon HVX IEEE FP follows this order:\n+ * QNaN > SNaN > +Inf > numbers > -Inf > SNaN_neg > QNaN_neg\n+ */\n+static bool float32_nan_compare(float32 f1, float32 f2, float_status *fp_status)\n+{\n+ /* opposite signs case */\n+ if (float32_is_neg(f1) != float32_is_neg(f2)) {\n+ return !float32_is_neg(f1);\n+ }\n+\n+ /* same sign case */\n+ bool result = (float32_is_any_nan(f1) && !float32_is_any_nan(f2)) ||\n+ (float32_is_quiet_nan(f1, fp_status) && !float32_is_quiet_nan(f2, fp_status));\n+ return float32_is_neg(f1) ? !result : result;\n+}\n+\n+static bool float16_nan_compare(float16 f1, float16 f2, float_status *fp_status)\n+{\n+ /* opposite signs case */\n+ if (float16_is_neg(f1) != float16_is_neg(f2)) {\n+ return !float16_is_neg(f1);\n+ }\n+\n+ /* same sign case */\n+ bool result = (float16_is_any_nan(f1) && !float16_is_any_nan(f2)) ||\n+ (float16_is_quiet_nan(f1, fp_status) && !float16_is_quiet_nan(f2, fp_status));\n+ return float16_is_neg(f1) ? !result : result;\n+}\n+\n+uint32_t cmpgt_sf(float32 a1, float32 a2, float_status *fp_status)\n+{\n+ if (float32_is_any_nan(a1) || float32_is_any_nan(a2)) {\n+ return float32_nan_compare(a1, a2, fp_status);\n+ }\n+ return float32_compare(a1, a2, fp_status) == float_relation_greater;\n+}\n+\n+uint16_t cmpgt_hf(float16 a1, float16 a2, float_status *fp_status)\n+{\n+ if (float16_is_any_nan(a1) || float16_is_any_nan(a2)) {\n+ return float16_nan_compare(a1, a2, fp_status);\n+ }\n+ return float16_compare(a1, a2, fp_status) == float_relation_greater;\n+}\ndiff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/imported/mmvec/encode_ext.def\nindex c1ed1b6c23..3572e4de4c 100644\n--- a/target/hexagon/imported/mmvec/encode_ext.def\n+++ b/target/hexagon/imported/mmvec/encode_ext.def\n@@ -858,4 +858,14 @@ DEF_ENC(V6_vconv_w_sf,\"00011110--0--101PP1uuuuu001ddddd\")\n DEF_ENC(V6_vconv_hf_h,\"00011110--0--101PP1uuuuu100ddddd\")\n DEF_ENC(V6_vconv_h_hf,\"00011110--0--101PP1uuuuu010ddddd\")\n \n+/* IEEE FP compare instructions */\n+DEF_ENC(V6_vgtsf,\"00011100100vvvvvPP1uuuuu011100dd\")\n+DEF_ENC(V6_vgthf,\"00011100100vvvvvPP1uuuuu011101dd\")\n+DEF_ENC(V6_vgtsf_and,\"00011100100vvvvvPP1uuuuu110010xx\")\n+DEF_ENC(V6_vgthf_and,\"00011100100vvvvvPP1uuuuu110011xx\")\n+DEF_ENC(V6_vgtsf_or,\"00011100100vvvvvPP1uuuuu001100xx\")\n+DEF_ENC(V6_vgthf_or,\"00011100100vvvvvPP1uuuuu001101xx\")\n+DEF_ENC(V6_vgtsf_xor,\"00011100100vvvvvPP1uuuuu111010xx\")\n+DEF_ENC(V6_vgthf_xor,\"00011100100vvvvvPP1uuuuu111011xx\")\n+\n #endif /* NO MMVEC */\ndiff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/imported/mmvec/ext.idef\nindex 788ce1d2ae..a7043d598c 100644\n--- a/target/hexagon/imported/mmvec/ext.idef\n+++ b/target/hexagon/imported/mmvec/ext.idef\n@@ -3143,6 +3143,67 @@ ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_hf_h,\"Vd32.hf=Vu32.h\",\n \"Vector conversion of int hw format to hf16\",\n VdV.hf[i] = float16_val(int16_to_float16(VuV.h[i], &env->hvx_fp_status)))\n \n+/******************************************************************************\n+ * IEEE FP compare instructions\n+ ******************************************************************************/\n+\n+#define VCMPGT_SF(DEST, ASRC, ASRCOP, CMP, N, SRC, MASK, WIDTH) \\\n+{ \\\n+ for (fHIDE(int) i = 0; i < fVBYTES(); i += WIDTH) { \\\n+ fHIDE(int) VAL = fCMPGT_SF(VuV.SRC[i/WIDTH],VvV.SRC[i/WIDTH]) ? MASK : 0; \\\n+ fSETQBITS(DEST,WIDTH,MASK,i,ASRC ASRCOP VAL); \\\n+ } \\\n+}\n+\n+#define VCMPGT_HF(DEST, ASRC, ASRCOP, CMP, N, SRC, MASK, WIDTH) \\\n+{ \\\n+ for (fHIDE(int) i = 0; i < fVBYTES(); i += WIDTH) { \\\n+ fHIDE(int) VAL = fCMPGT_HF(VuV.SRC[i/WIDTH],VvV.SRC[i/WIDTH]) ? MASK : 0; \\\n+ fSETQBITS(DEST,WIDTH,MASK,i,ASRC ASRCOP VAL); \\\n+ } \\\n+}\n+\n+/* Vector SF compare */\n+#define MMVEC_CMPGT_SF(TYPE,TYPE2,DESCR,N,MASK,WIDTH,SRC) \\\n+ EXTINSN(V6_vgt##TYPE##_and, \"Qx4&=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\", \\\n+ ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+ DESCR\" greater than with predicate-and\", \\\n+ VCMPGT_SF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), &, \">\", N, SRC, MASK, WIDTH)) \\\n+ EXTINSN(V6_vgt##TYPE##_xor, \"Qx4^=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\", \\\n+ ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+ DESCR\" greater than with predicate-xor\", \\\n+ VCMPGT_SF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), ^, \">\", N, SRC, MASK, WIDTH)) \\\n+ EXTINSN(V6_vgt##TYPE##_or, \"Qx4|=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\", \\\n+ ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+ DESCR\" greater than with predicate-or\", \\\n+ VCMPGT_SF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), |, \">\", N, SRC, MASK, WIDTH)) \\\n+ EXTINSN(V6_vgt##TYPE, \"Qd4=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\", \\\n+ ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+ DESCR\" greater than\", \\\n+ VCMPGT_SF(QdV, , , \">\", N, SRC, MASK, WIDTH))\n+\n+/* Vector HF compare */\n+#define MMVEC_CMPGT_HF(TYPE,TYPE2,DESCR,N,MASK,WIDTH,SRC) \\\n+ EXTINSN(V6_vgt##TYPE##_and, \"Qx4&=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\", \\\n+ ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+ DESCR\" greater than with predicate-and\", \\\n+ VCMPGT_HF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), &, \">\", N, SRC, MASK, WIDTH)) \\\n+ EXTINSN(V6_vgt##TYPE##_xor, \"Qx4^=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\", \\\n+ ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+ DESCR\" greater than with predicate-xor\", \\\n+ VCMPGT_HF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), ^, \">\", N, SRC, MASK, WIDTH)) \\\n+ EXTINSN(V6_vgt##TYPE##_or, \"Qx4|=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\", \\\n+ ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+ DESCR\" greater than with predicate-or\", \\\n+ VCMPGT_HF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), |, \">\", N, SRC, MASK, WIDTH)) \\\n+ EXTINSN(V6_vgt##TYPE, \"Qd4=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\", \\\n+ ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+ DESCR\" greater than\", \\\n+ VCMPGT_HF(QdV, , , \">\", N, SRC, MASK, WIDTH))\n+\n+MMVEC_CMPGT_SF(sf,\"sf\",\"Vector sf Compare \", fVELEM(32), 0xF, 4, sf)\n+MMVEC_CMPGT_HF(hf,\"hf\",\"Vector hf Compare \", fVELEM(16), 0x3, 2, hf)\n+\n /******************************************************************************\n DEBUG Vector/Register Printing\n ******************************************************************************/\n","prefixes":["v5","10/16"]}