{"id":2223913,"url":"http://patchwork.ozlabs.org/api/patches/2223913/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1a253373567781e0e141c34b41eaffad4789a493.1776339451.git.matheus.bernardino@oss.qualcomm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1a253373567781e0e141c34b41eaffad4789a493.1776339451.git.matheus.bernardino@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-16T11:39:00","name":"[v5,11/16] target/hexagon: add v73 HVX IEEE bfloat16 insns","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1515a58d66c749cf383e8dfa0b0425d78d245eb9","submitter":{"id":90606,"url":"http://patchwork.ozlabs.org/api/people/90606/?format=json","name":"Matheus Tavares Bernardino","email":"matheus.bernardino@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1a253373567781e0e141c34b41eaffad4789a493.1776339451.git.matheus.bernardino@oss.qualcomm.com/mbox/","series":[{"id":500137,"url":"http://patchwork.ozlabs.org/api/series/500137/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500137","date":"2026-04-16T11:38:50","name":"hexagon: add missing HVX float instructions","version":5,"mbox":"http://patchwork.ozlabs.org/series/500137/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223913/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223913/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=XNHuF1/b;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=ZqJsvypT;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n 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","To":"qemu-devel@nongnu.org","Cc":"richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com","Subject":"[PATCH v5 11/16] target/hexagon: add v73 HVX IEEE bfloat16 insns","Date":"Thu, 16 Apr 2026 04:39:00 -0700","Message-Id":"\n <1a253373567781e0e141c34b41eaffad4789a493.1776339451.git.matheus.bernardino@oss.qualcomm.com>","X-Mailer":"git-send-email 2.37.2","In-Reply-To":"","References":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-ORIG-GUID":"rh4KWNM-Sralvu7FqobG5CB5uerhOsk3","X-Proofpoint-GUID":"rh4KWNM-Sralvu7FqobG5CB5uerhOsk3","X-Authority-Analysis":"v=2.4 cv=XOIAjwhE c=1 sm=1 tr=0 ts=69e0ca69 cx=c_pps\n a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 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","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add HVX IEEE bfloat16 (bf16) instructions:\n\nArithmetic operations:\n- V6_vadd_sf_bf, V6_vsub_sf_bf: add/sub bf16 widening to sf output\n- V6_vmpy_sf_bf: multiply bf16 widening to sf output\n- V6_vmpy_sf_bf_acc: multiply-accumulate bf16 widening to sf output\n\nMin/Max operations:\n- V6_vmin_bf, V6_vmax_bf: bf16 min/max\n\nComparison operations:\n- V6_vgtbf: greater-than compare\n- V6_vgtbf_and, V6_vgtbf_or, V6_vgtbf_xor: predicate variants\n\nConversion operations:\n- V6_vcvt_bf_sf: convert sf to bf16\n\nReviewed-by: Taylor Simpson \nSigned-off-by: Matheus Tavares Bernardino \n---\n target/hexagon/mmvec/hvx_ieee_fp.h | 37 ++++++++++++\n target/hexagon/mmvec/macros.h | 4 ++\n target/hexagon/mmvec/mmvec.h | 1 +\n target/hexagon/imported/mmvec/encode_ext.def | 15 +++++\n target/hexagon/imported/mmvec/ext.idef | 62 ++++++++++++++++++++\n 5 files changed, 119 insertions(+)","diff":"diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_ieee_fp.h\nindex 01728121eb..b7e379b089 100644\n--- a/target/hexagon/mmvec/hvx_ieee_fp.h\n+++ b/target/hexagon/mmvec/hvx_ieee_fp.h\n@@ -9,8 +9,11 @@\n \n #include \"fpu/softfloat.h\"\n \n+#define FP32_DEF_NAN 0x7FFFFFFF\n+\n #define f16_to_f32(A) float16_to_float32((A), true, &env->hvx_fp_status)\n #define f32_to_f16(A) float32_to_float16((A), true, &env->hvx_fp_status)\n+#define bf16_to_f32(A) bfloat16_to_float32(A, &env->hvx_fp_status)\n \n float32 fp_mult_sf_hf(float16 a1, float16 a2, float_status *fp_status);\n float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, float16 a4,\n@@ -29,4 +32,38 @@ int16_t conv_h_hf(float16 a, float_status *fp_status);\n uint32_t cmpgt_sf(float32 a1, float32 a2, float_status *fp_status);\n uint16_t cmpgt_hf(float16 a1, float16 a2, float_status *fp_status);\n \n+/* IEEE BFloat instructions */\n+\n+#define fp_mult_sf_bf(A, B) \\\n+ float32_mul(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status)\n+\n+#define fp_add_sf_bf(A, B) \\\n+ float32_add(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status)\n+\n+#define fp_sub_sf_bf(A, B) \\\n+ float32_sub(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status)\n+\n+#define fp_mult_sf_bf_acc(f1, f2, f3) \\\n+ float32_muladd(bf16_to_f32(f1), bf16_to_f32(f2), f3, 0, &env->hvx_fp_status)\n+\n+static inline bfloat16 f32_to_bf16(float32 A, float_status *fp_status)\n+{\n+ uint32_t rslt = A;\n+ if ((rslt & 0x1FFFF) == 0x08000) {\n+ /* do not round up if exactly .5 and even already */\n+ } else if ((rslt & 0x8000) == 0x8000) {\n+ rslt += 0x8000; /* rounding to nearest number */\n+ }\n+ rslt = float32_is_any_nan(A) ? FP32_DEF_NAN : rslt;\n+ return float32_to_bfloat16(rslt, fp_status);\n+}\n+\n+#define fp_min_bf(A, B) \\\n+ f32_to_bf16(float32_min(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status), \\\n+ &env->hvx_fp_status);\n+\n+#define fp_max_bf(A, B) \\\n+ f32_to_bf16(float32_max(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status), \\\n+ &env->hvx_fp_status);\n+\n #endif\ndiff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h\nindex 318d44efb7..4945a61194 100644\n--- a/target/hexagon/mmvec/macros.h\n+++ b/target/hexagon/mmvec/macros.h\n@@ -25,6 +25,9 @@\n #include \"accel/tcg/probe.h\"\n #include \"mmvec/hvx_ieee_fp.h\"\n \n+#define fBFLOAT()\n+#define fCVI_VX_NO_TMP_LD()\n+\n #ifndef QEMU_GENERATE\n #define VdV (*(MMVector *restrict)(VdV_void))\n #define VsV (*(MMVector *restrict)(VsV_void))\n@@ -358,5 +361,6 @@\n \n #define fCMPGT_SF(A, B) cmpgt_sf(A, B, &env->hvx_fp_status)\n #define fCMPGT_HF(A, B) cmpgt_hf(A, B, &env->hvx_fp_status)\n+#define fCMPGT_BF(A, B) fCMPGT_SF((uint32_t)(A) << 16, (uint32_t)(B) << 16)\n \n #endif\ndiff --git a/target/hexagon/mmvec/mmvec.h b/target/hexagon/mmvec/mmvec.h\nindex 31909303b5..ab991471b1 100644\n--- a/target/hexagon/mmvec/mmvec.h\n+++ b/target/hexagon/mmvec/mmvec.h\n@@ -40,6 +40,7 @@ typedef union {\n int8_t b[MAX_VEC_SIZE_BYTES / 1];\n float32 sf[MAX_VEC_SIZE_BYTES / 4];\n float16 hf[MAX_VEC_SIZE_BYTES / 2];\n+ bfloat16 bf[MAX_VEC_SIZE_BYTES / 2];\n } MMVector;\n \n typedef union {\ndiff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/imported/mmvec/encode_ext.def\nindex 3572e4de4c..16f043b77d 100644\n--- a/target/hexagon/imported/mmvec/encode_ext.def\n+++ b/target/hexagon/imported/mmvec/encode_ext.def\n@@ -868,4 +868,19 @@ DEF_ENC(V6_vgthf_or,\"00011100100vvvvvPP1uuuuu001101xx\")\n DEF_ENC(V6_vgtsf_xor,\"00011100100vvvvvPP1uuuuu111010xx\")\n DEF_ENC(V6_vgthf_xor,\"00011100100vvvvvPP1uuuuu111011xx\")\n \n+/* BFLOAT instructions */\n+DEF_ENC(V6_vmpy_sf_bf,\"00011101010vvvvvPP1uuuuu100ddddd\")\n+DEF_ENC(V6_vmpy_sf_bf_acc,\"00011101000vvvvvPP1uuuuu000xxxxx\")\n+DEF_ENC(V6_vadd_sf_bf,\"00011101010vvvvvPP1uuuuu110ddddd\")\n+DEF_ENC(V6_vsub_sf_bf,\"00011101010vvvvvPP1uuuuu101ddddd\")\n+DEF_ENC(V6_vmax_bf,\"00011101010vvvvvPP1uuuuu111ddddd\")\n+DEF_ENC(V6_vmin_bf,\"00011101010vvvvvPP1uuuuu000ddddd\")\n+DEF_ENC(V6_vcvt_bf_sf,\"00011101010vvvvvPP1uuuuu011ddddd\")\n+\n+/* BFLOAT compare instructions */\n+DEF_ENC(V6_vgtbf,\"00011100100vvvvvPP1uuuuu011110dd\")\n+DEF_ENC(V6_vgtbf_and,\"00011100100vvvvvPP1uuuuu110100xx\")\n+DEF_ENC(V6_vgtbf_or,\"00011100100vvvvvPP1uuuuu001110xx\")\n+DEF_ENC(V6_vgtbf_xor,\"00011100100vvvvvPP1uuuuu111100xx\")\n+\n #endif /* NO MMVEC */\ndiff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/imported/mmvec/ext.idef\nindex a7043d598c..857aa6133f 100644\n--- a/target/hexagon/imported/mmvec/ext.idef\n+++ b/target/hexagon/imported/mmvec/ext.idef\n@@ -3163,6 +3163,15 @@ ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_hf_h,\"Vd32.hf=Vu32.h\",\n } \\\n }\n \n+#define VCMPGT_BF(DEST, ASRC, ASRCOP, CMP, N, SRC, MASK, WIDTH) \\\n+{ \\\n+ fBFLOAT(); \\\n+ for (fHIDE(int) i = 0; i < fVBYTES(); i += WIDTH) { \\\n+ fHIDE(int) VAL = fCMPGT_BF(VuV.SRC[i/WIDTH],VvV.SRC[i/WIDTH]) ? MASK : 0; \\\n+ fSETQBITS(DEST,WIDTH,MASK,i,ASRC ASRCOP VAL); \\\n+ } \\\n+}\n+\n /* Vector SF compare */\n #define MMVEC_CMPGT_SF(TYPE,TYPE2,DESCR,N,MASK,WIDTH,SRC) \\\n EXTINSN(V6_vgt##TYPE##_and, \"Qx4&=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\", \\\n@@ -3201,8 +3210,61 @@ ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_hf_h,\"Vd32.hf=Vu32.h\",\n DESCR\" greater than\", \\\n VCMPGT_HF(QdV, , , \">\", N, SRC, MASK, WIDTH))\n \n+/* Vector BF compare */\n+#define MMVEC_CMPGT_BF(TYPE,TYPE2,DESCR,N,MASK,WIDTH,SRC) \\\n+ EXTINSN(V6_vgt##TYPE##_and, \"Qx4&=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\",\\\n+ ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+ DESCR\" greater than with predicate-and\", \\\n+ VCMPGT_BF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), &, \">\", N, SRC, MASK, WIDTH)) \\\n+ EXTINSN(V6_vgt##TYPE##_xor, \"Qx4^=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\", \\\n+ ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+ DESCR\" greater than with predicate-xor\", \\\n+ VCMPGT_BF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), ^, \">\", N, SRC, MASK, WIDTH)) \\\n+ EXTINSN(V6_vgt##TYPE##_or, \"Qx4|=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\", \\\n+ ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+ DESCR\" greater than with predicate-or\", \\\n+ VCMPGT_BF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), |, \">\", N, SRC, MASK, WIDTH)) \\\n+ EXTINSN(V6_vgt##TYPE, \"Qd4=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\", \\\n+ ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+ DESCR\" greater than\", \\\n+ VCMPGT_BF(QdV, , , \">\", N, SRC, MASK, WIDTH))\n+\n MMVEC_CMPGT_SF(sf,\"sf\",\"Vector sf Compare \", fVELEM(32), 0xF, 4, sf)\n MMVEC_CMPGT_HF(hf,\"hf\",\"Vector hf Compare \", fVELEM(16), 0x3, 2, hf)\n+MMVEC_CMPGT_BF(bf,\"bf\",\"Vector bf Compare \", fVELEM(16), 0x3, 2, bf)\n+\n+/******************************************************************************\n+ BFloat arithmetic and max/min instructions\n+ ******************************************************************************/\n+\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vadd_sf_bf,\n+ \"Vdd32.sf=vadd(Vu32.bf,Vv32.bf)\", \"Vector IEEE add: bf widen to sf\",\n+ VddV.v[0].sf[i] = fp_add_sf_bf(VuV.bf[2*i], VvV.bf[2*i]);\n+ VddV.v[1].sf[i] = fp_add_sf_bf(VuV.bf[2*i+1], VvV.bf[2*i+1]); fBFLOAT())\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vsub_sf_bf,\n+ \"Vdd32.sf=vsub(Vu32.bf,Vv32.bf)\", \"Vector IEEE sub: bf widen to sf\",\n+ VddV.v[0].sf[i] = fp_sub_sf_bf(VuV.bf[2*i], VvV.bf[2*i]);\n+ VddV.v[1].sf[i] = fp_sub_sf_bf(VuV.bf[2*i+1], VvV.bf[2*i+1]); fBFLOAT())\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vmpy_sf_bf,\n+ \"Vdd32.sf=vmpy(Vu32.bf,Vv32.bf)\", \"Vector IEEE mul: hf widen to sf\",\n+ VddV.v[0].sf[i] = fp_mult_sf_bf(VuV.bf[2*i], VvV.bf[2*i]);\n+ VddV.v[1].sf[i] = fp_mult_sf_bf(VuV.bf[2*i+1], VvV.bf[2*i+1]); fBFLOAT())\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vmpy_sf_bf_acc,\n+ \"Vxx32.sf+=vmpy(Vu32.bf,Vv32.bf)\", \"Vector IEEE fma: hf widen to sf\",\n+ VxxV.v[0].sf[i] = fp_mult_sf_bf_acc(VuV.bf[2*i], VvV.bf[2*i], VxxV.v[0].sf[i]);\n+ VxxV.v[1].sf[i] = fp_mult_sf_bf_acc(VuV.bf[2*i+1], VvV.bf[2*i+1], VxxV.v[1].sf[i]);\n+ fCVI_VX_NO_TMP_LD(); fBFLOAT())\n+ITERATOR_INSN_IEEE_FP_16(32, vcvt_bf_sf,\n+ \"Vd32.bf=vcvt(Vu32.sf,Vv32.sf)\", \"Vector IEEE cvt: sf to bf\",\n+ VdV.bf[2*i] = f32_to_bf16(VuV.sf[i], &env->hvx_fp_status);\n+ VdV.bf[2*i+1] = f32_to_bf16(VvV.sf[i], &env->hvx_fp_status); fBFLOAT())\n+\n+ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vmax_bf, \"Vd32.bf=vmax(Vu32.bf,Vv32.bf)\",\n+ \"Vector IEEE max: bf\", VdV.bf[i] = fp_max_bf(VuV.bf[i], VvV.bf[i]);\n+ fBFLOAT())\n+ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vmin_bf, \"Vd32.bf=vmin(Vu32.bf,Vv32.bf)\",\n+ \"Vector IEEE min: bf\", VdV.bf[i] = fp_min_bf(VuV.bf[i], VvV.bf[i]);\n+ fBFLOAT())\n \n /******************************************************************************\n DEBUG Vector/Register Printing\n","prefixes":["v5","11/16"]}