{"id":2223912,"url":"http://patchwork.ozlabs.org/api/patches/2223912/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/8f9a2e2ccfd2eeda73a63d1a6abbfd6e5458b44c.1776339451.git.matheus.bernardino@oss.qualcomm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<8f9a2e2ccfd2eeda73a63d1a6abbfd6e5458b44c.1776339451.git.matheus.bernardino@oss.qualcomm.com>","list_archive_url":null,"date":"2026-04-16T11:38:53","name":"[v5,04/16] hexagon: group cpu configurations in their own struct","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"26ea5c655d2a38ecce9ddea56cc0a310ee537ac3","submitter":{"id":90606,"url":"http://patchwork.ozlabs.org/api/people/90606/?format=json","name":"Matheus Tavares Bernardino","email":"matheus.bernardino@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/8f9a2e2ccfd2eeda73a63d1a6abbfd6e5458b44c.1776339451.git.matheus.bernardino@oss.qualcomm.com/mbox/","series":[{"id":500137,"url":"http://patchwork.ozlabs.org/api/series/500137/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500137","date":"2026-04-16T11:38:50","name":"hexagon: add missing HVX float instructions","version":5,"mbox":"http://patchwork.ozlabs.org/series/500137/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223912/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223912/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=NRreBNDX;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=e7r13KwR;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n 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","To":"qemu-devel@nongnu.org","Cc":"richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com","Subject":"[PATCH v5 04/16] hexagon: group cpu configurations in their own\n struct","Date":"Thu, 16 Apr 2026 04:38:53 -0700","Message-Id":"\n <8f9a2e2ccfd2eeda73a63d1a6abbfd6e5458b44c.1776339451.git.matheus.bernardino@oss.qualcomm.com>","X-Mailer":"git-send-email 2.37.2","In-Reply-To":"","References":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDE2MDExMCBTYWx0ZWRfX27yTu/YaTXpV\n nj6RWIgkKuNplm610I80sqK29d2cQq5dd9533yGjHdmzVg9lDR0DacETb6rK+7zKUuGCIPSQcD1\n bry1nYH+047OADH7rGiGMTrIOns+yNwqaXC4gFbQjvOAS7HNhbRnKPJ/TIKpSu2L0WRq30AgPFr\n w3aKKks+7ja4mfuRbgZK4L56BloJy8bujzO+G1kgGfijk5HXNYDSuCbcIOhe0cV5lZy2Tjstn+/\n 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","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This will be used in a follow up commit.\n\nReviewed-by: Taylor Simpson \nSigned-off-by: Matheus Tavares Bernardino \n---\n target/hexagon/cpu.h | 10 +++-------\n target/hexagon/cpu_bits.h | 7 +++++++\n target/hexagon/cpu.c | 14 +++++++-------\n target/hexagon/translate.c | 6 +++---\n 4 files changed, 20 insertions(+), 17 deletions(-)","diff":"diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h\nindex 77822a48b6..d28beaa92f 100644\n--- a/target/hexagon/cpu.h\n+++ b/target/hexagon/cpu.h\n@@ -119,19 +119,15 @@ typedef struct HexagonCPUClass {\n ResettablePhases parent_phases;\n } HexagonCPUClass;\n \n+#include \"cpu_bits.h\"\n+\n struct ArchCPU {\n CPUState parent_obj;\n \n CPUHexagonState env;\n-\n- bool lldb_compat;\n- target_ulong lldb_stack_adjust;\n- bool short_circuit;\n- bool ieee_fp_extension;\n+ HexagonCPUConfig cfg;\n };\n \n-#include \"cpu_bits.h\"\n-\n FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)\n \n G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,\ndiff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h\nindex 19beca81c0..83d13de569 100644\n--- a/target/hexagon/cpu_bits.h\n+++ b/target/hexagon/cpu_bits.h\n@@ -20,6 +20,13 @@\n \n #include \"qemu/bitops.h\"\n \n+typedef struct HexagonCPUConfig {\n+ bool lldb_compat;\n+ uint32_t lldb_stack_adjust;\n+ bool short_circuit;\n+ bool ieee_fp_extension;\n+} HexagonCPUConfig;\n+\n #define PCALIGN 4\n #define PCALIGN_MASK (PCALIGN - 1)\n \ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex 8b72a5d3c8..5470d9c7ce 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -50,11 +50,11 @@ static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)\n }\n \n static const Property hexagon_cpu_properties[] = {\n- DEFINE_PROP_BOOL(\"lldb-compat\", HexagonCPU, lldb_compat, false),\n- DEFINE_PROP_UNSIGNED(\"lldb-stack-adjust\", HexagonCPU, lldb_stack_adjust, 0,\n- qdev_prop_uint32, target_ulong),\n- DEFINE_PROP_BOOL(\"short-circuit\", HexagonCPU, short_circuit, true),\n- DEFINE_PROP_BOOL(\"ieee-fp\", HexagonCPU, ieee_fp_extension, true),\n+ DEFINE_PROP_BOOL(\"lldb-compat\", HexagonCPU, cfg.lldb_compat, false),\n+ DEFINE_PROP_UNSIGNED(\"lldb-stack-adjust\", HexagonCPU, cfg.lldb_stack_adjust,\n+ 0, qdev_prop_uint32, target_ulong),\n+ DEFINE_PROP_BOOL(\"short-circuit\", HexagonCPU, cfg.short_circuit, true),\n+ DEFINE_PROP_BOOL(\"ieee-fp\", HexagonCPU, cfg.ieee_fp_extension, true),\n };\n \n const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {\n@@ -77,7 +77,7 @@ const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {\n static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr)\n {\n HexagonCPU *cpu = env_archcpu(env);\n- target_ulong stack_adjust = cpu->lldb_stack_adjust;\n+ target_ulong stack_adjust = cpu->cfg.lldb_stack_adjust;\n target_ulong stack_start = env->stack_start;\n target_ulong stack_size = 0x10000;\n \n@@ -181,7 +181,7 @@ static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags)\n {\n HexagonCPU *cpu = env_archcpu(env);\n \n- if (cpu->lldb_compat) {\n+ if (cpu->cfg.lldb_compat) {\n /*\n * When comparing with LLDB, it doesn't step through single-cycle\n * hardware loops the same way. So, we just skip them here\ndiff --git a/target/hexagon/translate.c b/target/hexagon/translate.c\nindex fa8f615a9e..ce3af96675 100644\n--- a/target/hexagon/translate.c\n+++ b/target/hexagon/translate.c\n@@ -987,8 +987,8 @@ static void hexagon_tr_init_disas_context(DisasContextBase *dcbase,\n ctx->num_hvx_insns = 0;\n ctx->branch_cond = TCG_COND_NEVER;\n ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP);\n- ctx->short_circuit = hex_cpu->short_circuit;\n- ctx->ieee_fp_extension = hex_cpu->ieee_fp_extension;\n+ ctx->short_circuit = hex_cpu->cfg.short_circuit;\n+ ctx->ieee_fp_extension = hex_cpu->cfg.ieee_fp_extension;\n }\n \n static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu)\n@@ -1041,7 +1041,7 @@ static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu)\n * so end the TLB after every packet.\n */\n HexagonCPU *hex_cpu = env_archcpu(env);\n- if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) {\n+ if (hex_cpu->cfg.lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) {\n ctx->base.is_jmp = DISAS_TOO_MANY;\n }\n }\n","prefixes":["v5","04/16"]}