{"id":2223898,"url":"http://patchwork.ozlabs.org/api/patches/2223898/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260416111422.183860-12-sherry.sun@nxp.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260416111422.183860-12-sherry.sun@nxp.com>","list_archive_url":null,"date":"2026-04-16T11:14:21","name":"[V13,11/12] arm64: dts: imx8dxl/qm/qxp: Add Root Port node and PERST property","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"abba5f1ba9856206e772e59eeef6d23581b4ea95","submitter":{"id":77063,"url":"http://patchwork.ozlabs.org/api/people/77063/?format=json","name":"Sherry Sun","email":"sherry.sun@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260416111422.183860-12-sherry.sun@nxp.com/mbox/","series":[{"id":500134,"url":"http://patchwork.ozlabs.org/api/series/500134/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=500134","date":"2026-04-16T11:14:11","name":"pci-imx6: Add support for parsing the reset property in new Root Port binding","version":13,"mbox":"http://patchwork.ozlabs.org/series/500134/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223898/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223898/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com 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","To":"robh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tFrank.Li@nxp.com,\n\ts.hauer@pengutronix.de,\n\tkernel@pengutronix.de,\n\tfestevam@gmail.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tbhelgaas@google.com,\n\thongxing.zhu@nxp.com,\n\tl.stach@pengutronix.de","Cc":"imx@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Subject":"[PATCH V13 11/12] arm64: dts: imx8dxl/qm/qxp: Add Root Port node and\n PERST property","Date":"Thu, 16 Apr 2026 19:14:21 +0800","Message-Id":"<20260416111422.183860-12-sherry.sun@nxp.com>","X-Mailer":"git-send-email 2.37.1","In-Reply-To":"<20260416111422.183860-1-sherry.sun@nxp.com>","References":"<20260416111422.183860-1-sherry.sun@nxp.com>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"MA0PR01CA0076.INDPRD01.PROD.OUTLOOK.COM\n (2603:1096:a01:ad::17) To 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pY7iXQ55SKXiGHaCfxPThPBeA8+TuaB3UrFJnMBxGsQp1xAEGY/UaI9TV8sxj2q8wowz8S0uQ1OQeqRdBxIhlrCpUupl44Xg1wWM16mKAsfFRknUCk1gRV07cCHSH71dh0Qd2VFRSobgymS0RtICQuDg70abbIriqK3lXyu33WI5XBcTtXQZPKOpP1eccWpd1C26TQ4fANsz+MMJeyUNinIsZ2yVThjLT7yH7rE6UxOuGNYGNcfWNx4mnrDHEJrPtpXZWs4X3HlBNXlDAUfMkEGpLnFVvwVAzJ2IfDoK9ZbGBQUpjD63KR9Y/5lKaSEyJgRcphC0E6zM4Tadg72uHRU5KghdqMEQ/HiaclPel7LgixSepqSTAAB7eD84bBXApPFVRoI2gaaiQhcGO6s610KlbaZq90le7L8hiXvn81dtw/pGa84xeD6VgZKqGfvfPkPiO68/5osuSKxgPrr/nlSVWjO/G8HmTb1r8zKRe0z9hstz9Df8lx5szDdHELjwJPvUjja3oN4Ops9AOy8AUy1IpYxU5rJpcd8m3opnm6xDuV0wuw6CYSl3mod5BDQILh5w94Gkg2r77+he6+5vPZonzb7Ak6mSiO/KN9A3Z0XkFyLnPlHZknYgymZM/buLQZKfsudYyc7UC/4wWMrRX1pqwAheZEWRWgrxCmdp57Og/W/LJui3mg8LLYpFQ6HAVPXvjzYahxk+qsLCogYfaHKVzQNKGCej2NDUD9DQp5di+sYkU9zVUFjTk2Ogry4U3AO6pDv0XeQY2SEetaFWanV2pzWg0hcVFrBPyXSXvxCHvkAWN73IvexNR1cjhi4ZUbe2jEvG3g7urwdd8Cbq20KWSv9zxfQyxxjAvooC2aUaUKBvqBruG2ykaEX2CpvPoPncBc2jJvoZXaehZzJFl4w87KS8Aaw4QLtUOYjgWK0I1V5oLUQ1Mx+nfWFC3Tr1falFxZUN0yyDVWZymCTj8BEtFSOwpvObKSh040AXo02mhEsuwNOSlV93cU5dtk5SF7mJ2v9BpslDrBV1yHtNY6us9271BSR658WngQSLSj8sTkYWSbwdCM8/AK9D1Dmt/fk6P3CQpMxXICZULmU2EdiC8KE4eD5cgW7bj8KKx7tZaSAtdI0NXV4+1kH4pa/bJOoY+QCT5J8nm+cpyWdTvoDBSpzu2SChunGyZvhcChEm4Ryh8Mz13bkLFTGvAxGvTJ4C0iCs8YySfgbOnUURSEOa2HlqDtYFSCTMBswwrPUAecJqKKwYlRhTR7RDzYsxQADKT2JmOaFFtgJIxNdK0IgAlLcnN35p7qwh2CylZjiyB+b5SS+VxiiQprx6FM3d4H1SCxgmOi2V5lYo14y2FUVPZ9hzoqWB6KY7cFN+WQZMtXe2iBi4d1XMkADmTStdSgm6YDNNnB5P5/RttV5N1BN0rz+flZJoE8jhRlaBt/6Anae8LWGsHBlDLuoXXm1Osfmv6CD3IEIs5QpcvVzcK/MMW1nk11jTB4HCZrgnEOQMnz8wcj+J+KuTCY0UVsOukwQlNLefQbnCVI/a91DiBvkMELZl+/IrkN/Nau7cWKVdYfss7ldnrrYZgDoGj0cbCGx4oFp9/tLBRExxtUUKdcksvLTqQ6zKu2wiCKB6Dyj4tOSyNY23vlsHN0Kf0pkhfkMCG0RyXQ6OngQGQrWxs2jYHC+m1I2yB5patTw2uI3slj0OuBZjXCtOAMv9qNuX8I14xDXmz+niFZXpCKmh4A==","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 444c33e5-1f10-41bd-e9e3-08de9ba94850","X-MS-Exchange-CrossTenant-AuthSource":"VI0PR04MB12114.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"16 Apr 2026 11:14:10.0548\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n iT6oiNFDli2orpVGR2r5IX3FJ9b3eO+JrtdFXkbcSTshd8P9PNFKeacbKFtS2YA6f6304bubJs/OTgB4fV9dRw==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DBBPR04MB7897"},"content":"Since describing the PCIe PERST# property under Host Bridge node is now\ndeprecated, it is recommended to add it to the Root Port node, so\ncreating the Root Port node and add the reset-gpios property in Root\nPort.\n\nSigned-off-by: Sherry Sun \n---\n .../boot/dts/freescale/imx8-ss-hsio.dtsi | 11 ++++++++++\n arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 5 +++++\n arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 10 +++++++++\n .../boot/dts/freescale/imx8qm-ss-hsio.dtsi | 22 +++++++++++++++++++\n arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 5 +++++\n 5 files changed, 53 insertions(+)","diff":"diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi\nindex 469de8b536b5..009990b2e559 100644\n--- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi\n+++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi\n@@ -78,6 +78,17 @@ pcieb: pcie@5f010000 {\n \t\tpower-domains = <&pd IMX_SC_R_PCIE_B>;\n \t\tfsl,max-link-speed = <3>;\n \t\tstatus = \"disabled\";\n+\n+\t\tpcieb_port0: pcie@0 {\n+\t\t\tcompatible = \"pciclass,0604\";\n+\t\t\tdevice_type = \"pci\";\n+\t\t\treg = <0x0 0x0 0x0 0x0 0x0>;\n+\t\t\tbus-range = <0x01 0xff>;\n+\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\t\t};\n \t};\n \n \tpcieb_ep: pcie-ep@5f010000 {\ndiff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts\nindex bc62ae5ca812..39108a915f96 100644\n--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts\n+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts\n@@ -675,6 +675,7 @@ &pcie0 {\n \tphy-names = \"pcie-phy\";\n \tpinctrl-0 = <&pinctrl_pcieb>;\n \tpinctrl-names = \"default\";\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;\n \tvpcie-supply = <®_pcieb>;\n \tvpcie3v3aux-supply = <®_pcieb>;\n@@ -691,6 +692,10 @@ &pcie0_ep {\n \tstatus = \"disabled\";\n };\n \n+&pcieb_port0 {\n+\treset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;\n+};\n+\n &sai0 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_sai0>;\ndiff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts\nindex 011a89d85961..f706c86137c0 100644\n--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts\n+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts\n@@ -810,6 +810,7 @@ &pciea {\n \tphy-names = \"pcie-phy\";\n \tpinctrl-0 = <&pinctrl_pciea>;\n \tpinctrl-names = \"default\";\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;\n \tvpcie-supply = <®_pciea>;\n \tvpcie3v3aux-supply = <®_pciea>;\n@@ -817,15 +818,24 @@ &pciea {\n \tstatus = \"okay\";\n };\n \n+&pciea_port0 {\n+\treset-gpios = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;\n+};\n+\n &pcieb {\n \tphys = <&hsio_phy 1 PHY_TYPE_PCIE 1>;\n \tphy-names = \"pcie-phy\";\n \tpinctrl-0 = <&pinctrl_pcieb>;\n \tpinctrl-names = \"default\";\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;\n \tstatus = \"disabled\";\n };\n \n+&pcieb_port0 {\n+\treset-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;\n+};\n+\n &qm_pwm_lvds0 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_pwm_lvds0>;\ndiff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi\nindex f2c94cdb682b..2e4fbfe0ca16 100644\n--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi\n+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi\n@@ -41,6 +41,17 @@ pcie0: pciea: pcie@5f000000 {\n \t\tpower-domains = <&pd IMX_SC_R_PCIE_A>;\n \t\tfsl,max-link-speed = <3>;\n \t\tstatus = \"disabled\";\n+\n+\t\tpciea_port0: pcie@0 {\n+\t\t\tcompatible = \"pciclass,0604\";\n+\t\t\tdevice_type = \"pci\";\n+\t\t\treg = <0x0 0x0 0x0 0x0 0x0>;\n+\t\t\tbus-range = <0x01 0xff>;\n+\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\t\t};\n \t};\n \n \tpcie0_ep: pciea_ep: pcie-ep@5f000000 {\n@@ -91,6 +102,17 @@ pcie1: pcieb: pcie@5f010000 {\n \t\tpower-domains = <&pd IMX_SC_R_PCIE_B>;\n \t\tfsl,max-link-speed = <3>;\n \t\tstatus = \"disabled\";\n+\n+\t\tpcieb_port0: pcie@0 {\n+\t\t\tcompatible = \"pciclass,0604\";\n+\t\t\tdevice_type = \"pci\";\n+\t\t\treg = <0x0 0x0 0x0 0x0 0x0>;\n+\t\t\tbus-range = <0x01 0xff>;\n+\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\t\t};\n \t};\n \n \tsata: sata@5f020000 {\ndiff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts\nindex 623169f7ddb5..489e174df4c4 100644\n--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts\n+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts\n@@ -730,6 +730,7 @@ &pcie0 {\n \tphy-names = \"pcie-phy\";\n \tpinctrl-0 = <&pinctrl_pcieb>;\n \tpinctrl-names = \"default\";\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;\n \tvpcie-supply = <®_pcieb>;\n \tvpcie3v3aux-supply = <®_pcieb>;\n@@ -746,6 +747,10 @@ &pcie0_ep {\n \tstatus = \"disabled\";\n };\n \n+&pcieb_port0 {\n+\treset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;\n+};\n+\n &scu_key {\n \tstatus = \"okay\";\n };\n","prefixes":["V13","11/12"]}