{"id":2223418,"url":"http://patchwork.ozlabs.org/api/patches/2223418/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/patch/20260415095020.1597-1-dongxuyang@eswincomputing.com/","project":{"id":38,"url":"http://patchwork.ozlabs.org/api/projects/38/?format=json","name":"Linux PWM development","link_name":"linux-pwm","list_id":"linux-pwm.vger.kernel.org","list_email":"linux-pwm@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415095020.1597-1-dongxuyang@eswincomputing.com>","list_archive_url":null,"date":"2026-04-15T09:50:20","name":"[v4,1/2] dt-bindings: pwm: dwc: add reset optional","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"9f2748bde6c2b124c8069a9ee46d3234624b432b","submitter":{"id":90849,"url":"http://patchwork.ozlabs.org/api/people/90849/?format=json","name":"Xuyang Dong","email":"dongxuyang@eswincomputing.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pwm/patch/20260415095020.1597-1-dongxuyang@eswincomputing.com/mbox/","series":[{"id":499954,"url":"http://patchwork.ozlabs.org/api/series/499954/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/list/?series=499954","date":"2026-04-15T09:49:08","name":"Update designware pwm driver","version":4,"mbox":"http://patchwork.ozlabs.org/series/499954/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223418/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223418/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n <linux-pwm+bounces-8584-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776246652; cv=none;\n b=pIkOXjfPrvubMxGbgQ4KVyNzXGS+1jBESQj5xSbRxLtuNN5nDOw9GOMh1FuBZ3jFaDdZAcGLy8eGVUSnndgcoa9EZwsLVviy5kwZjq3PXQwBXTZ2OU0SqaAmKfFHhKMnuUAxvpqXLC8MPKAIQIjfOp2ByvDOPaBF/OSiqCzTYkw=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776246652; c=relaxed/simple;\n\tbh=8IQa4cY03S5QfTv0xJSuJITE5Sln/HnAKl65dub12L0=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:\n\t MIME-Version;\n b=eYc+YlFforFwnKqe5zdJybqH+6XZCx/VFaqdbHK9eFo+XANJfRfAs7fWW8/5USSoCTk9N0QWIpmiZhHcmUs6rVrhRMgvEBDbqCx2r2SJxpVzbtK8s3CsSgWdphwv7bQFhXGyvf7gqBfolMgc+H9uY32hgNTNuvRQfgkVSnOC2v8=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=none (p=none dis=none) header.from=eswincomputing.com;\n spf=pass smtp.mailfrom=eswincomputing.com;\n arc=none smtp.client-ip=52.175.55.52","From":"dongxuyang@eswincomputing.com","To":"ukleinek@kernel.org,\n\trobh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tben-linux@fluff.org,\n\tben.dooks@codethink.co.uk,\n\tp.zabel@pengutronix.de,\n\tlinux-pwm@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Cc":"ningyu@eswincomputing.com,\n\tlinmin@eswincomputing.com,\n\txuxiang@eswincomputing.com,\n\twangguosheng@eswincomputing.com,\n\tpinkesh.vaghela@einfochips.com,\n\tXuyang Dong <dongxuyang@eswincomputing.com>","Subject":"[PATCH v4 1/2] dt-bindings: pwm: dwc: add reset optional","Date":"Wed, 15 Apr 2026 17:50:20 +0800","Message-Id":"<20260415095020.1597-1-dongxuyang@eswincomputing.com>","X-Mailer":"git-send-email 2.31.1.windows.1","In-Reply-To":"<20260415094908.1539-1-dongxuyang@eswincomputing.com>","References":"<20260415094908.1539-1-dongxuyang@eswincomputing.com>","Precedence":"bulk","X-Mailing-List":"linux-pwm@vger.kernel.org","List-Id":"<linux-pwm.vger.kernel.org>","List-Subscribe":"<mailto:linux-pwm+subscribe@vger.kernel.org>","List-Unsubscribe":"<mailto:linux-pwm+unsubscribe@vger.kernel.org>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-CM-TRANSID":"TQJkCgDX7aBgX99pTuMRAA--.14964S2","X-Coremail-Antispam":"1UD129KBjvdXoWruF4UtFWkGrWDAryUCrW8Xrb_yoWkJrc_uF\n\t4fZan8WFW5JFyrKrs8tr4xJF1Yyw17GF4kJrn8KFn7u3Wqk3yUWr95tryUury7Wan3uFyr\n\tuFWftr9rtrnrKjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT\n\t9fnUUIcSsGvfJTRUUUbhxFF20E14v26r4j6ryUM7CY07I20VC2zVCF04k26cxKx2IYs7xG\n\t6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8w\n\tA2z4x0Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j\n\t6F4UJwA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oV\n\tCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0\n\tI7IYx2IY67AKxVWUAVWUtwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r\n\t4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628v\n\tn2kIc2xKxwAKzVCY07xG64k0F24lc7CjxVAaw2AFwI0_Jw0_GFylc2xSY4AK6svPMxAIw2\n\t8IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4l\n\tx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVW8ZVWrXwCIc40Y0x0EwIxGrw\n\tCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI\n\t42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z2\n\t80aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbQJ57UUUUU==","X-CM-SenderInfo":"pgrqw5xx1d0w46hv4xpqfrz1xxwl0woofrz/"},"content":"From: Xuyang Dong <dongxuyang@eswincomputing.com>\n\nThe DesignWare PWM includes separate reset signals dedicated to each clock\ndomain:\nThe presetn signal resets logic in pclk domain.\nThe timer_N_resetn signal resets logic in the timer_N_clk domain.\nThe resets are active-low.\n\nSigned-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>\n---\n .../devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml       | 3 +++\n 1 file changed, 3 insertions(+)","diff":"diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\nindex 7523a89a1773..a8bbad0360f8 100644\n--- a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\n+++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml\n@@ -43,6 +43,9 @@ properties:\n       - const: bus\n       - const: timer\n \n+  resets:\n+    maxItems: 2\n+\n   snps,pwm-number:\n     $ref: /schemas/types.yaml#/definitions/uint32\n     description: The number of PWM channels configured for this instance\n","prefixes":["v4","1/2"]}