{"id":2223409,"url":"http://patchwork.ozlabs.org/api/patches/2223409/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260415090959.53672-3-fengchengwen@huawei.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415090959.53672-3-fengchengwen@huawei.com>","list_archive_url":null,"date":"2026-04-15T09:09:57","name":"[2/4] vfio/pci: Add PCIe TPH enable/disable support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"644b7d1308d37f8c445f512b6fefc5429799bdae","submitter":{"id":92756,"url":"http://patchwork.ozlabs.org/api/people/92756/?format=json","name":"fengchengwen","email":"fengchengwen@huawei.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260415090959.53672-3-fengchengwen@huawei.com/mbox/","series":[{"id":499948,"url":"http://patchwork.ozlabs.org/api/series/499948/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=499948","date":"2026-04-15T09:09:55","name":"vfio/pci: Add PCIe TPH support","version":1,"mbox":"http://patchwork.ozlabs.org/series/499948/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223409/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223409/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256\n header.s=dkim header.b=ZIfTXnMv;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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a=rsa-sha256; d=huawei.com; s=dkim;\n\tc=relaxed/relaxed; q=dns/txt;\n\th=From;\n\tbh=rJcrzVYEdZvWn4l1GSbvteU9PPixNTbKyDINkLeZZdY=;\n\tb=ZIfTXnMvHhfuKh+8Gdqo/fQ9UzKPQ9fn7qvDu092XdRzxNmpdc6gNyaTMb3NMMdDww/fqel5f\n\t/wum9wMxB7/aCXPUNqixN6Q1YQlysIVtW97JBVYw+bnJejR4yipdg084Rss8D2PgzYcLwVwREUN\n\tAFW/8kHjYdyzV5bTIBEnM+s=","From":"Chengwen Feng ","To":", ","CC":", ,\n\t, Chengwen Feng ","Subject":"[PATCH 2/4] vfio/pci: Add PCIe TPH enable/disable support","Date":"Wed, 15 Apr 2026 17:09:57 +0800","Message-ID":"<20260415090959.53672-3-fengchengwen@huawei.com>","X-Mailer":"git-send-email 2.17.1","In-Reply-To":"<20260415090959.53672-1-fengchengwen@huawei.com>","References":"<20260415090959.53672-1-fengchengwen@huawei.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain","X-ClientProxiedBy":"kwepems200001.china.huawei.com (7.221.188.67) To\n kwepemk500009.china.huawei.com (7.202.194.94)"},"content":"Add support to enable and disable TPH function with\nmode selection.\n\nSigned-off-by: Chengwen Feng \n---\n drivers/vfio/pci/vfio_pci_core.c | 35 ++++++++++++++++++++++++++++++++\n 1 file changed, 35 insertions(+)","diff":"diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c\nindex 35df624439a3..0f96b41779cd 100644\n--- a/drivers/vfio/pci/vfio_pci_core.c\n+++ b/drivers/vfio/pci/vfio_pci_core.c\n@@ -1493,6 +1493,37 @@ static int vfio_pci_tph_get_cap(struct vfio_pci_core_device *vdev,\n #endif\n }\n \n+static int vfio_pci_tph_enable(struct vfio_pci_core_device *vdev,\n+\t\t\t struct vfio_device_pci_tph_op *op,\n+\t\t\t void __user *uarg)\n+{\n+\tstruct vfio_pci_tph_ctrl ctrl;\n+\tint mode;\n+\n+\tif (op->argsz < offsetofend(struct vfio_device_pci_tph_op, ctrl))\n+\t\treturn -EINVAL;\n+\n+\tif (copy_from_user(&ctrl, uarg, sizeof(ctrl)))\n+\t\treturn -EFAULT;\n+\n+\tif (ctrl.mode != VFIO_PCI_TPH_MODE_IV && ctrl.mode != VFIO_PCI_TPH_MODE_DS)\n+\t\treturn -EINVAL;\n+\n+\t/* Reserved must be zero */\n+\tif (memchr_inv(ctrl.reserved, 0, sizeof(ctrl.reserved)))\n+\t\treturn -EINVAL;\n+\n+\tmode = (ctrl.mode == VFIO_PCI_TPH_MODE_IV) ? PCI_TPH_ST_IV_MODE :\n+\t\t\t\t\t\t PCI_TPH_ST_DS_MODE;\n+\treturn pcie_enable_tph(vdev->pdev, mode);\n+}\n+\n+static int vfio_pci_tph_disable(struct vfio_pci_core_device *vdev)\n+{\n+\tpcie_disable_tph(vdev->pdev);\n+\treturn 0;\n+}\n+\n static int vfio_pci_ioctl_tph(struct vfio_pci_core_device *vdev,\n \t\t\t void __user *uarg)\n {\n@@ -1509,6 +1540,10 @@ static int vfio_pci_ioctl_tph(struct vfio_pci_core_device *vdev,\n \tswitch (op.op) {\n \tcase VFIO_PCI_TPH_GET_CAP:\n \t\treturn vfio_pci_tph_get_cap(vdev, &op, uarg + minsz);\n+\tcase VFIO_PCI_TPH_ENABLE:\n+\t\treturn vfio_pci_tph_enable(vdev, &op, uarg + minsz);\n+\tcase VFIO_PCI_TPH_DISABLE:\n+\t\treturn vfio_pci_tph_disable(vdev);\n \tdefault:\n \t\t/* Other ops are not implemented yet */\n \t\treturn -EINVAL;\n","prefixes":["2/4"]}