{"id":2223405,"url":"http://patchwork.ozlabs.org/api/patches/2223405/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260415-10g-v1-2-f6809a31c2b2@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415-10g-v1-2-f6809a31c2b2@nxp.com>","list_archive_url":null,"date":"2026-04-15T08:56:27","name":"[v1,2/2] net: fsl_enetc: Add iMX95 enetc4 10Gbps port support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3e54a85c4c1aab9399a62bc489842f96fdb73493","submitter":{"id":80695,"url":"http://patchwork.ozlabs.org/api/people/80695/?format=json","name":"Alice Guo (OSS)","email":"alice.guo@oss.nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260415-10g-v1-2-f6809a31c2b2@nxp.com/mbox/","series":[{"id":499947,"url":"http://patchwork.ozlabs.org/api/series/499947/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=499947","date":"2026-04-15T08:56:25","name":"net: fsl_enetc: Add iMX95 10Gbps support and PHY fixes","version":1,"mbox":"http://patchwork.ozlabs.org/series/499947/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223405/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223405/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector1-NXP1-onmicrosoft-com\n header.b=FGc+sghP;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Add optional serdes-supply regulator property support.\n2. Enable 10Gbps feature for the controller, configure netc blkctrl\n CFG_LINK_PCS_PROT_2 to 10G SXGMII.\n3. Add internal xpcs phy initialization to 10G XGMII Mode without\n auto-negotiation interface.\n\nSigned-off-by: Ye Li \nSigned-off-by: Alice Guo \n---\n drivers/net/fsl_enetc.c | 57 ++-\n drivers/net/fsl_enetc.h | 1 +\n drivers/net/fsl_enetc_xpcs_phy.c | 970 +++++++++++++++++++++++++++++++++++++++\n 3 files changed, 1017 insertions(+), 11 deletions(-)","diff":"diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c\nindex a4ba27904bc..206f1a381bb 100644\n--- a/drivers/net/fsl_enetc.c\n+++ b/drivers/net/fsl_enetc.c\n@@ -8,6 +8,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \n@@ -20,14 +21,21 @@\n #include \n #include \n #include \n+#include \n+#include \n+#include \"fsl_enetc.h\"\n \n #ifdef CONFIG_ARCH_IMX9\n #include \n #include \n+#include \"fsl_enetc_xpcs_phy.c\"\n+#else\n+static inline int xpcs_phy_usxgmii_pma_config(struct udevice *dev)\n+{\n+\treturn 0;\n+}\n #endif\n \n-#include \"fsl_enetc.h\"\n-\n #define ENETC_DRIVER_NAME\t\"enetc_eth\"\n \n /*\n@@ -454,19 +462,23 @@ static void enetc_setup_mac_iface(struct udevice *dev,\n /* set up serdes for SXGMII */\n static int enetc_init_sxgmii(struct udevice *dev)\n {\n-\tstruct enetc_priv *priv = dev_get_priv(dev);\n-\n \tif (!enetc_has_imdio(dev))\n \t\treturn 0;\n \n-\t/* Dev ability - SXGMII */\n-\tenetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,\n-\t\t\t ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);\n+\tif (enetc_is_imx95(dev)) {\n+\t\txpcs_phy_usxgmii_pma_config(dev);\n+\t} else {\n+\t\tstruct enetc_priv *priv = dev_get_priv(dev);\n+\n+\t\t/* Dev ability - SXGMII */\n+\t\tenetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,\n+\t\t\t\t ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);\n \n-\t/* Restart PCS AN */\n-\tenetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,\n-\t\t\t ENETC_PCS_CR,\n-\t\t\t ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);\n+\t\t/* Restart PCS AN */\n+\t\tenetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,\n+\t\t\t\t ENETC_PCS_CR,\n+\t\t\t\t ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);\n+\t}\n \n \treturn 0;\n }\n@@ -523,6 +535,10 @@ static int enetc_config_phy(struct udevice *dev)\n \t\treturn -ENODEV;\n \n \tsupported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;\n+\n+\tif (enetc_is_imx95(dev))\n+\t\tsupported |= PHY_10G_FEATURES;\n+\n \tpriv->phy->supported &= supported;\n \tpriv->phy->advertising &= supported;\n \n@@ -537,12 +553,31 @@ static int enetc_probe(struct udevice *dev)\n {\n \tstruct enetc_priv *priv = dev_get_priv(dev);\n \tint res;\n+\tstruct udevice *supply = NULL;\n \n \tif (ofnode_valid(dev_ofnode(dev)) && !ofnode_is_enabled(dev_ofnode(dev))) {\n \t\tenetc_dbg(dev, \"interface disabled\\n\");\n \t\treturn -ENODEV;\n \t}\n \n+\tif (CONFIG_IS_ENABLED(DM_REGULATOR)) {\n+\t\tres = device_get_supply_regulator(dev, \"serdes-supply\",\n+\t\t\t\t\t\t &supply);\n+\t\tif (res && res != -ENOENT) {\n+\t\t\tprintf(\"%s: device_get_supply_regulator failed: %d\\n\",\n+\t\t\t __func__, res);\n+\t\t\treturn res;\n+\t\t}\n+\n+\t\tif (supply) {\n+\t\t\tres = regulator_set_enable_if_allowed(supply, true);\n+\t\t\tif (res) {\n+\t\t\t\tprintf(\"%s: Error enabling phy supply\\n\", dev->name);\n+\t\t\t\treturn res;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n \tpriv->enetc_txbd = memalign(ENETC_BD_ALIGN,\n \t\t\t\t sizeof(struct enetc_tx_bd) * ENETC_BD_CNT);\n \tpriv->enetc_rxbd = memalign(ENETC_BD_ALIGN,\ndiff --git a/drivers/net/fsl_enetc.h b/drivers/net/fsl_enetc.h\nindex 804df853bf5..6d868e82f8c 100644\n--- a/drivers/net/fsl_enetc.h\n+++ b/drivers/net/fsl_enetc.h\n@@ -205,6 +205,7 @@ struct enetc_data {\n \n /* PCS / internal SoC PHY ID, it defaults to 0 on all interfaces */\n #define ENETC_PCS_PHY_ADDR\t0\n+#define ENETC_NON_PCS_PHY_ADDR 16\n \n /* PCS registers */\n #define ENETC_PCS_CR\t\t\t0x00\ndiff --git a/drivers/net/fsl_enetc_xpcs_phy.c b/drivers/net/fsl_enetc_xpcs_phy.c\nnew file mode 100644\nindex 00000000000..4039690223d\n--- /dev/null\n+++ b/drivers/net/fsl_enetc_xpcs_phy.c\n@@ -0,0 +1,970 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright 2024 NXP\n+ */\n+\n+#define XPCS_PHY_GLOBAL\t\t0x0\n+#define XPCS_PHY_MPLLA\t\t0x1\n+#define XPCS_PHY_MPLLB\t\t0x2\n+#define XPCS_PHY_LANE\t\t0x3\n+#define XPCS_PHY_MAC_ADAPTER\t0x1f\n+\n+#define XPCS_PHY_REG(x) (((x) & 0x1fffe) >> 1)\n+\n+/* MAC ADAPTER */\n+#define MAC_ADAPTER_LOCK_PHY\t0x200\n+#define MAC_ADAPTER_LOCK_MPLLA\t0x204\n+#define MAC_ADAPTER_LOCK_MPLLB\t0x208\n+#define MAC_ADAPTER_LOCK_ROM\t0x20c\n+#define MAC_ADAPTER_LOCK_RAM\t0x210\n+#define MAC_ADAPTER_LOCK_EVENT\t0x214\n+\n+#define MAC_ADAPTER_LOCK_LOCK\tBIT(7)\n+\n+/* PMA */\n+#define PMA_RX_LSTS\t\t\t\t\t0x10040\n+#define PMA_RX_LSTS_RX_VALID_0\t\t\tBIT(12)\n+#define PMA_MP_12G_16G_25G_TX_GENCTRL0\t\t\t0x10060\n+#define PMA_TX_GENCTRL0_TX_RST_0\t\tBIT(8)\n+#define PMA_TX_GENCTRL0_TX_DT_EN_0\t\tBIT(12)\n+#define PMA_MP_12G_16G_25G_TX_GENCTRL1\t\t\t0x10062\n+#define PMA_TX_GENCTRL1_VBOOST_EN_0\t\tBIT(4)\n+#define PMA_TX_GENCTRL1_VBOOST_LVL_MASK\t\tGENMASK(10, 8)\n+#define PMA_TX_GENCTRL1_VBOOST_LVL(x)\t\t(((x) << 8) & GENMASK(10, 8))\n+#define PMA_TX_GENCTRL1_TX_CLK_RDY_0\t\tBIT(12)\n+#define PMA_MP_12G_16G_TX_GENCTRL2\t\t\t0x10064\n+#define PMA_TX_GENCTRL2_TX_REQ_0\t\tBIT(0)\n+#define PMA_TX_GENCTRL2_TX0_WIDTH_MASK\t\tGENMASK(9, 8)\n+#define PMA_TX_GENCTRL2_TX0_WIDTH(x)\t\t(((x) << 8) & GENMASK(9, 8))\n+#define PMA_MP_12G_16G_25G_TX_BOOST_CTRL\t\t0x10066\n+#define PMA_TX_BOOST_CTRL_TX0_IBOOST_MASK\tGENMASK(3, 0)\n+#define PMA_TX_BOOST_CTRL_TX0_IBOOST(x)\t\t((x) & GENMASK(3, 0))\n+#define PMA_MP_12G_16G_25G_TX_RATE_CTRL\t\t\t0x10068\n+#define PMA_TX_RATE_CTRL_TX0_RATE_MASK\t\tGENMASK(2, 0)\n+#define PMA_TX_RATE_CTRL_TX0_RATE(x)\t\t((x) & GENMASK(2, 0))\n+#define PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL\t\t0x1006A\n+#define PMA_POWER_STATE_CTRL_TX0_PSTATE_MASK\tGENMASK(1, 0)\n+#define PMA_POWER_STATE_CTRL_TX0_PSTATE(x)\t((x) & GENMASK(1, 0))\n+#define PMA_POWER_STATE_CTRL_TX_DISABLE_0\tBIT(8)\n+#define PMA_MP_12G_16G_25G_TX_EQ_CTRL0\t\t\t0x1006C\n+#define PMA_TX_EQ_CTRL0_TX_EQ_PRE_MASK\t\tGENMASK(5, 0)\n+#define PMA_TX_EQ_CTRL0_TX_EQ_PRE(x)\t\t((x) & GENMASK(5, 0))\n+#define PMA_TX_EQ_CTRL0_TX_EQ_MAIN_MASK\t\tGENMASK(13, 8)\n+#define PMA_TX_EQ_CTRL0_TX_EQ_MAIN(x)\t\t(((x) << 8) & GENMASK(13, 8))\n+#define PMA_MP_12G_16G_25G_TX_EQ_CTRL1\t\t\t0x1006E\n+#define PMA_TX_EQ_CTRL1_TX_EQ_POST_MASK\t\tGENMASK(5, 0)\n+#define PMA_TX_EQ_CTRL1_TX_EQ_POST(x)\t\t((x) & GENMASK(5, 0))\n+#define PMA_MP_16G_25G_TX_MISC_CTRL0\t\t\t0x1007C\n+#define PMA_TX_MISC_CTRL0_TX0_MISC_MASK\t\tGENMASK(7, 0)\n+#define PMA_TX_MISC_CTRL0_TX0_MISC(x)\t\t((x) & GENMASK(7, 0))\n+#define PMA_MP_12G_16G_25G_RX_GENCTRL0\t\t\t0x100A0\n+#define PMA_RX_GENCTRL0_RX_DT_EN_0\t\tBIT(8)\n+#define PMA_MP_12G_16G_25G_RX_GENCTRL1\t\t\t0x100A2\n+#define PMA_RX_GENCTRL1_RX_RST_0\t\tBIT(4)\n+#define PMA_RX_GENCTRL1_RX_TERM_ACDC_0\t\tBIT(8)\n+#define PMA_RX_GENCTRL1_RX_DIV16P5_CLK_EN_0\tBIT(12)\n+#define PMA_MP_12G_16G_RX_GENCTRL2\t\t\t0x100A4\n+#define PMA_RX_GENCTRL2_RX_REQ_0\t\tBIT(0)\n+#define PMA_RX_GENCTRL2_RX0_WIDTH_MASK\t\tGENMASK(9, 8)\n+#define PMA_RX_GENCTRL2_RX0_WIDTH(x)\t\t(((x) << 8) & GENMASK(9, 8))\n+#define PMA_MP_12G_16G_RX_GENCTRL3\t\t\t0x100A6\n+#define PMA_RX_GENCTRL3_LOS_TRSHLD_0_MASK\tGENMASK(2, 0)\n+#define PMA_RX_GENCTRL3_LOS_TRSHLD_0(x)\t\t((x) & GENMASK(2, 0))\n+#define PMA_RX_GENCTRL3_LOS_LFPS_EN_0\t\tBIT(12)\n+#define PMA_MP_12G_16G_25G_RX_RATE_CTRL\t\t\t0x100A8\n+#define PMA_RX_RATE_CTRL_RX0_RATE_MASK\t\tGENMASK(1, 0)\n+#define PMA_RX_RATE_CTRL_RX0_RATE(x)\t\t((x) & GENMASK(1, 0))\n+#define PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL\t\t0x100AA\n+#define PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK\tGENMASK(1, 0)\n+#define PMA_RX_POWER_STATE_CTRL_RX0_PSTATE(x)\t((x) & GENMASK(1, 0))\n+#define PMA_RX_POWER_STATE_CTRL_RX_DISABLE_0\tBIT(8)\n+#define PMA_MP_12G_16G_25G_RX_CDR_CTRL\t\t\t0x100AC\n+#define PMA_RX_CDR_CTRL_CDR_SSC_EN_0\t\tBIT(4)\n+#define PMA_MP_12G_16G_25G_RX_ATTN_CTRL\t\t\t0x100AE\n+#define PMA_RX_ATTN_CTRL_RX0_EQ_ATT_LVL_MASK\tGENMASK(2, 0)\n+#define PMA_RX_ATTN_CTRL_RX0_EQ_ATT_LVL(x)\t((x) & GENMASK(2, 0))\n+#define PMA_MP_16G_25G_RX_EQ_CTRL0\t\t\t0x100B0\n+#define PMA_RX_EQ_CTRL0_CTLE_BOOST_0_MASK\tGENMASK(4, 0)\n+#define PMA_RX_EQ_CTRL0_CTLE_BOOST_0(x)\t\t((x) & GENMASK(4, 0))\n+#define PMA_RX_EQ_CTRL0_CTLE_POLE_0_MASK\tGENMASK(6, 5)\n+#define PMA_RX_EQ_CTRL0_CTLE_POLE_0(x)\t\t(((x) << 5) & GENMASK(6, 5))\n+#define PMA_RX_EQ_CTRL0_VGA2_GAIN_0_MASK\tGENMASK(10, 8)\n+#define PMA_RX_EQ_CTRL0_VGA2_GAIN_0(x)\t\t(((x) << 8) & GENMASK(10, 8))\n+#define PMA_RX_EQ_CTRL0_VGA1_GAIN_0_MASK\tGENMASK(14, 12)\n+#define PMA_RX_EQ_CTRL0_VGA1_GAIN_0(x)\t\t(((x) << 12) & GENMASK(14, 12))\n+#define PMA_MP_12G_16G_25G_RX_EQ_CTRL4\t\t\t0x100B8\n+#define PMA_RX_EQ_CTRL4_CONT_ADAPT_0\t\tBIT(0)\n+#define PMA_RX_EQ_CTRL4_RX_AD_REQ\t\tBIT(12)\n+#define PMA_MP_16G_25G_RX_EQ_CTRL5\t\t\t0x100BA\n+#define PMA_RX_EQ_CTRL5_RX_ADPT_SEL_0\t\tBIT(0)\n+#define PMA_RX_EQ_CTRL5_RX0_ADPT_MODE_MASK\tGENMASK(5, 4)\n+#define PMA_RX_EQ_CTRL5_RX0_ADPT_MODE(x)\t(((x) << 4) & GENMASK(5, 4))\n+#define PMA_MP_12G_16G_25G_DFE_TAP_CTRL0\t\t0x100BC\n+#define PMA_DFE_TAP_CTRL0_DFE_TAP1_0_MASK\tGENMASK(7, 0)\n+#define PMA_DFE_TAP_CTRL0_DFE_TAP1_0(x)\t\t((x) & GENMASK(7, 0))\n+#define PMA_MP_16G_RX_CDR_CTRL1\t\t\t\t0x100C8\n+#define PMA_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0\tBIT(0)\n+#define PMA_RX_CDR_CTRL1_VCO_STEP_CTRL_0\tBIT(4)\n+#define PMA_RX_CDR_CTRL1_VCO_FRQBAND_0_MASK\tGENMASK(9, 8)\n+#define PMA_RX_CDR_CTRL1_VCO_FRQBAND_0(x)\t(((x) << 8) & GENMASK(9, 8))\n+#define PMA_MP_16G_25G_RX_PPM_CTRL0\t\t\t0x100CA\n+#define PMA_RX_PPM_CTRL0_RX0_CDR_PPM_MAX_MASK\tGENMASK(4, 0)\n+#define PMA_RX_PPM_CTRL0_RX0_CDR_PPM_MAX(x)\t((x) & GENMASK(4, 0))\n+#define PMA_MP_16G_25G_RX_GENCTRL4\t\t\t0x100D0\n+#define PMA_RX_GENCTRL4_RX_DFE_BYP_0\t\tBIT(8)\n+#define PMA_MP_16G_25G_RX_MISC_CTRL0\t\t\t0x100D2\n+#define PMA_RX_MISC_CTRL0_RX0_MISC_MASK\t\tGENMASK(7, 0)\n+#define PMA_RX_MISC_CTRL0_RX0_MISC(x)\t\t((x) & GENMASK(7, 0))\n+#define PMA_MP_16G_25G_RX_IQ_CTRL0\t\t\t0x100D6\n+#define PMA_RX_IQ_CTRL0_RX0_MARGIN_IQ_MASK\tGENMASK(6, 0)\n+#define PMA_RX_IQ_CTRL0_RX0_MARGIN_IQ(x)\t((x) & GENMASK(6, 0))\n+#define PMA_RX_IQ_CTRL0_RX0_DELTA_IQ_MASK\tGENMASK(11, 8)\n+#define PMA_RX_IQ_CTRL0_RX0_DELTA_IQ(x)\t\t(((x) << 8) & GENMASK(11, 8))\n+#define PMA_MP_12G_16G_25G_MPLL_CMN_CTRL\t\t0x100E0\n+#define PMA_MPLL_CMN_CTRL_MPLL_EN_0\t\tBIT(0)\n+#define PMA_MPLL_CMN_CTRL_MPLLB_SEL_0\t\tBIT(4)\n+#define PMA_MP_12G_16G_MPLLA_CTRL0\t\t\t0x100E2\n+#define PMA_MPLLA_CTRL0_MPLLA_MULTIPLIER_MASK\tGENMASK(7, 0)\n+#define PMA_MPLLA_CTRL0_MPLLA_MULTIPLIER(x)\t((x) & GENMASK(7, 0))\n+#define PMA_MP_16G_MPLLA_CTRL1\t\t\t\t0x100E4\n+#define PMA_MPLLA_CTRL1_MPLLA_SSC_EN\t\tBIT(0)\n+#define PMA_MPLLA_CTRL1_MPLLA_SSC_CLK_SEL\tBIT(4)\n+#define PMA_MPLLA_CTRL1_MPLLA_FRACN_CTRL_MASK\tGENMASK(15, 5)\n+#define PMA_MPLLA_CTRL1_MPLLA_FRACN_CTRL(x)\t(((x) << 5) & GENMASK(15, 5))\n+#define PMA_MP_12G_16G_MPLLA_CTRL2\t\t\t0x100E6\n+#define PMA_MPLLA_CTRL2_MPLLA_DIV_MULT_MASK\tGENMASK(6, 0)\n+#define PMA_MPLLA_CTRL2_MPLLA_DIV_MULT(x)\t((x) & GENMASK(6, 0))\n+#define PMA_MPLLA_CTRL2_MPLLA_DIV_CLK_EN\tBIT(7)\n+#define PMA_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN\tBIT(8)\n+#define PMA_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN\tBIT(9)\n+#define PMA_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN\tBIT(10)\n+#define PMA_MPLLA_CTRL2_MPLLA_TX_CLK_DIV_MASK\tGENMASK(12, 11)\n+#define PMA_MPLLA_CTRL2_MPLLA_TX_CLK_DIV(x)\t(((x) << 11) & GENMASK(12, 11))\n+#define PMA_MP_16G_MPLLA_CTRL3\t\t\t\t0x100EE\n+#define PMA_MPLLA_CTRL3_MPLLA_BANDWIDTH_MASK\tGENMASK(15, 0)\n+#define PMA_MPLLA_CTRL3_MPLLA_BANDWIDTH(x)\t((x) & GENMASK(15, 0))\n+#define PMA_MP_16G_MPLLA_CTRL4\t\t\t\t0x100F2\n+#define PMA_MPLLA_CTRL4_MPLLA_SSC_FRQ_CNT_INT_MASK GENMASK(11, 0)\n+#define PMA_MPLLA_CTRL4_MPLLA_SSC_FRQ_CNT_INT(x) ((x) & GENMASK(11, 0))\n+#define PMA_MP_16G_MPLLA_CTRL5\t\t\t\t0x100F4\n+#define PMA_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK_MASK GENMASK(7, 0)\n+#define PMA_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK(x)\t((x) & GENMASK(7, 0))\n+#define PMA_MPLLA_CTRL5_MPLLA_SSC_SPD_EN\tBIT(8)\n+#define PMA_MP_12G_16G_25G_MISC_CTRL0\t\t\t0x10120\n+#define PMA_MISC_CTRL0_RX_VREF_CTRL_MASK\tGENMASK(12, 8)\n+#define PMA_MISC_CTRL0_RX_VREF_CTRL(x)\t\t(((x) << 8) & GENMASK(12, 8))\n+#define PMA_MP_12G_16G_25G_REF_CLK_CTRL\t\t\t0x10122\n+#define PMA_REF_CLK_CTRL_REF_CLK_DIV2\t\tBIT(2)\n+#define PMA_REF_CLK_CTRL_REF_RANGE_MASK\t\tGENMASK(5, 3)\n+#define PMA_REF_CLK_CTRL_REF_RANGE(x)\t\t(((x) << 3) & GENMASK(5, 3))\n+#define PMA_REF_CLK_CTRL_REF_MPLLA_DIV2\t\tBIT(6)\n+#define PMA_MP_12G_16G_25G_VCO_CAL_LD0\t\t\t0x10124\n+#define PMA_VCO_CAL_LD0_VCO_LD_VAL_0_MASK\tGENMASK(12, 0)\n+#define PMA_VCO_CAL_LD0_VCO_LD_VAL_0(x)\t\t((x) & GENMASK(12, 0))\n+#define PMA_MP_16G_25G_VCO_CAL_REF0\t\t\t0x1012C\n+#define PMA_VCO_CAL_REF0_VCO_REF_LD_0_MASK\tGENMASK(6, 0)\n+#define PMA_VCO_CAL_REF0_VCO_REF_LD_0(x)\t((x) & GENMASK(6, 0))\n+#define PMA_MP_12G_16G_25G_MISC_STS\t\t\t0x10130\n+#define PMA_MISC_STS_RX_ADPT_ACK\t\tBIT(12)\n+#define PMA_MP_12G_16G_25G_SRAM\t\t\t\t0x10136\n+#define PMA_SRAM_INIT_DN\t\t\tBIT(0)\n+#define PMA_SRAM_EXT_LD_DN\t\t\tBIT(1)\n+#define PMA_MP_16G_25G_MISC_CTRL2\t\t\t0x10138\n+#define PMA_MISC_CTRL2_SUP_MISC_MASK\t\tGENMASK(7, 0)\n+#define PMA_MISC_CTRL2_SUP_MISC(x)\t\t((x) & GENMASK(7, 0))\n+\n+/* PCS */\n+#define PCS_CTRL1\t\t\t\t0x0\n+#define PCS_CTRL1_RESET\t\t\tBIT(15)\n+#define PCS_CTRL2\t\t\t\t0xE\n+#define PCS_CTRL2_PCS_TYPE_SEL_MASK\tGENMASK(3, 0)\n+#define PCS_CTRL2_PCS_TYPE_SEL(x)\t((x) & GENMASK(3, 0))\n+#define PCS_DIG_CTRL1\t\t\t\t0x10000\n+#define PCS_DIG_CTRL1_USXG_EN\t\tBIT(9)\n+#define PCS_DIG_CTRL1_USRA_RST\t\tBIT(10)\n+#define PCS_DIG_CTRL1_VR_RST\t\tBIT(15)\n+#define PCS_DEBUG_CTRL\t\t\t\t0x1000A\n+#define PCS_DEBUG_CTRL_SUPRESS_LOS_DET\tBIT(4)\n+#define PCS_DEBUG_CTRL_RX_DT_EN_CTL\tBIT(6)\n+#define PCS_DEBUG_CTRL_TX_PMBL_CTL\tBIT(8)\n+#define PCS_KR_CTRL1\t\t\t\t0x1000E\n+#define PCS_KR_CTRL1_USXG_MODE_MASK\tGENMASK(12, 10)\n+#define PCS_KR_CTRL1_USXG_MODE(x)\t(((x) << 10) & GENMASK(12, 10))\n+\n+/* VS MII MMD */\n+#define MII_CTRL\t\t\t\t\t0x0\n+#define MII_CTRL_SS5\t\t\t\tBIT(5)\n+#define MII_CTRL_SS6\t\t\t\tBIT(6)\n+#define MII_CTRL_AN_ENABLE\t\t\tBIT(12)\n+#define MII_CTRL_SS13\t\t\t\tBIT(13)\n+#define MII_DIG_CTRL1\t\t\t\t\t0x10000\n+#define MII_DIG_CTRL1_CL37_TMR_OVR_RIDE\t\tBIT(3)\n+#define MII_AN_CTRL\t\t\t\t\t0x10002\n+#define MII_AN_CTRL_MII_AN_INTR_EN\t\tBIT(0)\n+#define MII_AN_CTRL_TX_CONFIG\t\t\tBIT(3)\n+#define MII_AN_INTR_STS\t\t\t\t\t0x10004\n+#define MII_AN_INTR_STS_CL37_ANCMPLT_INTR\tBIT(0)\n+#define MII_LINK_TIMER_CTRL\t\t\t\t0x10014\n+#define MII_LINK_TIMER_CTRL_CL37_LINK_TIME_MASK\t\tGENMASK(15, 0)\n+#define MII_LINK_TIMER_CTRL_CL37_LINK_TIME(x)\t\t((x) & GENMASK(15, 0))\n+\n+/* E16 MEM MAP */\n+#define IDCODE_LO\t\t\t\t\t\t0x0\n+#define IDCODE_HI\t\t\t\t\t\t0x4\n+#define GLOBAL_CTRL_EX_0\t\t\t\t\t0x114\n+#define GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS\t\tBIT(0)\n+#define L0_RX_VCO_OVRD_OUT_0\t\t\t\t\t0x20c\n+#define L0_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_FREQ_TUNE_MASK\tGENMASK(12, 3)\n+#define L0_RX_VCO_OVRD_OUT_0_RX_ANA_CDR_FREQ_TUNE(x)\t(((x) << 3) & GENMASK(12, 3))\n+#define L0_RX_VCO_OVRD_OUT_0_RX_CDR_FREQ_TUNE_OVRD_EN\tBIT(15)\n+#define L0_RX_VCO_OVRD_OUT_2\t\t\t\t\t0x214\n+#define L0_RX_VCO_OVRD_OUT_2_RX_ANA_CDR_FREQ_TUNE_CLK\tBIT(0)\n+\n+static int enetc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg);\n+static int enetc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, u16 val);\n+\n+int xpcs_read(struct udevice *dev, int devaddr, u32 reg)\n+{\n+\tstruct enetc_priv *priv = dev_get_priv(dev);\n+\n+\treturn enetc_mdio_read(&priv->imdio, ENETC_PCS_PHY_ADDR, devaddr, reg);\n+}\n+\n+int xpcs_write(struct udevice *dev, int devaddr, u32 reg, u16 val)\n+{\n+\tstruct enetc_priv *priv = dev_get_priv(dev);\n+\n+\treturn enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, devaddr, reg, val);\n+}\n+\n+int xpcs_phy_read(struct udevice *dev, int devaddr, u32 reg)\n+{\n+\tstruct enetc_priv *priv = dev_get_priv(dev);\n+\n+\treturn enetc_mdio_read(&priv->imdio, ENETC_NON_PCS_PHY_ADDR, devaddr, reg);\n+}\n+\n+int xpcs_phy_write(struct udevice *dev, int devaddr, u32 reg, u16 val)\n+{\n+\tstruct enetc_priv *priv = dev_get_priv(dev);\n+\n+\treturn enetc_mdio_write(&priv->imdio, ENETC_NON_PCS_PHY_ADDR, devaddr, reg, val);\n+}\n+\n+int xpcs_phy_read_pma(struct udevice *dev, u32 reg)\n+{\n+\treturn xpcs_read(dev, MDIO_MMD_PMAPMD, XPCS_PHY_REG(reg));\n+}\n+\n+int xpcs_phy_write_pma(struct udevice *dev, int reg, u16 val)\n+{\n+\treturn xpcs_write(dev, MDIO_MMD_PMAPMD, XPCS_PHY_REG(reg), val);\n+}\n+\n+int xpcs_phy_usxgmii_init_seq_2(struct udevice *dev)\n+{\n+\tulong begin;\n+\tu16 val;\n+\n+\t/* Seq 2.1 Keep preamble data */\n+\tval = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL));\n+\tval |= PCS_DEBUG_CTRL_TX_PMBL_CTL;\n+\txpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL), val);\n+\n+\t/* Seq 2.2 Power up MPLLA to P1 state */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL);\n+\tval = u16_replace_bits(val, 2, PMA_POWER_STATE_CTRL_TX0_PSTATE_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL);\n+\tval |= PMA_MPLL_CMN_CTRL_MPLL_EN_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, val);\n+\n+\t/* Seq 2.3 Assert request of transmitand receive */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);\n+\tval |= PMA_TX_GENCTRL2_TX_REQ_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);\n+\tval |= PMA_RX_GENCTRL2_RX_REQ_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val);\n+\n+\t/* Seq 2.4 Poll for acknowledge */\n+\tbegin = get_timer(0);\n+\tdo {\n+\t\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);\n+\t\tif (get_timer(begin) > 500) {\n+\t\t\tdev_err(dev, \"Polling timeout, line: %d\\n\", __LINE__);\n+\t\t\tgoto timeout;\n+\t\t}\n+\t\tmdelay(10);\n+\t} while (val & PMA_TX_GENCTRL2_TX_REQ_0);\n+\n+\tbegin = get_timer(0);\n+\tdo {\n+\t\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);\n+\t\tif (get_timer(begin) > 500) {\n+\t\t\tdev_err(dev, \"Polling timeout, line: %d\\n\", __LINE__);\n+\t\t\tgoto timeout;\n+\t\t}\n+\t\tmdelay(10);\n+\t} while (val & PMA_RX_GENCTRL2_RX_REQ_0);\n+\n+\t/* Seq 2.5 Turn transmit to P0 state */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL);\n+\tval = u16_replace_bits(val, 0, PMA_POWER_STATE_CTRL_TX0_PSTATE_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0);\n+\tval &= ~PMA_TX_GENCTRL0_TX_RST_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL);\n+\tval &= ~PMA_POWER_STATE_CTRL_TX_DISABLE_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL);\n+\tval |= PMA_MPLL_CMN_CTRL_MPLL_EN_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, val);\n+\n+\t/* Seq 2.6 Turn receive to P0 state */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1);\n+\tval &= ~PMA_RX_GENCTRL1_RX_RST_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL);\n+\tval &= ~PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK;\n+\tval &= ~PMA_RX_POWER_STATE_CTRL_RX_DISABLE_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL);\n+\tval &= ~PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK;\n+\tval &= ~PMA_RX_POWER_STATE_CTRL_RX_DISABLE_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val);\n+\n+\t/* Seq 2.7 Enable transmitter output driver in the PHY */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0);\n+\tval |= PMA_TX_GENCTRL0_TX_DT_EN_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val);\n+\n+\t/* Seq 2.8 Enable receiver data output from PHY */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0);\n+\tval |= PMA_RX_GENCTRL0_RX_DT_EN_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0, val);\n+\n+\t/* Seq 2.9 Assert request of transmit and receive */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);\n+\tval |= PMA_TX_GENCTRL2_TX_REQ_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);\n+\tval |= PMA_RX_GENCTRL2_RX_REQ_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val);\n+\n+\t/* Seq 2.10 Poll for acknowledge */\n+\tbegin = get_timer(0);\n+\tdo {\n+\t\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);\n+\t\tif (get_timer(begin) > 500) {\n+\t\t\tdev_err(dev, \"Polling timeout, line: %d\\n\", __LINE__);\n+\t\t\tgoto timeout;\n+\t\t}\n+\t\tmdelay(10);\n+\t\tschedule();\n+\t} while (val & PMA_TX_GENCTRL2_TX_REQ_0);\n+\n+\tbegin = get_timer(0);\n+\tdo {\n+\t\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);\n+\t\tif (get_timer(begin) > 500) {\n+\t\t\tdev_err(dev, \"Polling timeout, line: %d\\n\", __LINE__);\n+\t\t\tgoto timeout;\n+\t\t}\n+\t\tmdelay(10);\n+\t\tschedule();\n+\t} while (val & PMA_RX_GENCTRL2_RX_REQ_0);\n+\n+\treturn 0;\n+\n+timeout:\n+\treturn -ETIMEDOUT;\n+}\n+\n+void xpcs_phy_reg_lock(struct udevice *dev)\n+{\n+\tu16 val;\n+\tulong begin;\n+\n+\tif (xpcs_phy_read(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_PHY)) & MAC_ADAPTER_LOCK_LOCK)\n+\t\treturn;\n+\n+\txpcs_phy_write(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_PHY), MAC_ADAPTER_LOCK_LOCK);\n+\txpcs_phy_write(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_MPLLA), MAC_ADAPTER_LOCK_LOCK);\n+\txpcs_phy_write(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_MPLLB), MAC_ADAPTER_LOCK_LOCK);\n+\txpcs_phy_write(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_ROM), MAC_ADAPTER_LOCK_LOCK);\n+\txpcs_phy_write(dev, XPCS_PHY_MAC_ADAPTER, XPCS_PHY_REG(MAC_ADAPTER_LOCK_RAM), MAC_ADAPTER_LOCK_LOCK);\n+\n+\tbegin = get_timer(0);\n+\tdo {\n+\t\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_SRAM);\n+\t\tif (get_timer(begin) > 500) {\n+\t\t\tdev_err(dev, \"Polling timeout, line: %d\\n\", __LINE__);\n+\t\t\tgoto timeout;\n+\t\t}\n+\t\tmdelay(10);\n+\t} while (!(val & PMA_SRAM_INIT_DN));\n+\n+\t/* Work around */\n+\t// xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_SRAM, PMA_SRAM_EXT_LD_DN);\n+\txpcs_phy_write(dev, XPCS_PHY_GLOBAL, XPCS_PHY_REG(GLOBAL_CTRL_EX_0), GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS);\n+\n+\tbegin = get_timer(0);\n+\tdo {\n+\t\tval = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_CTRL1));\n+\t\tif (get_timer(begin) > 500) {\n+\t\t\tdev_err(dev, \"Polling timeout, line: %d\\n\", __LINE__);\n+\t\t\tgoto timeout;\n+\t\t}\n+\t\tmdelay(10);\n+\t} while (val & PCS_CTRL1_RESET);\n+\n+\tmdelay(1);\n+\n+timeout:\n+\treturn;\n+}\n+\n+int xpcs_phy_usxgmii_pma_config(struct udevice *dev)\n+{\n+\tulong begin;\n+\tu16 val;\n+\n+\txpcs_phy_reg_lock(dev);\n+\n+\t/* 1.6 Turn off C37 auto-negotiation */\n+\tval = xpcs_read(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_CTRL));\n+\tval &= ~MII_CTRL_AN_ENABLE;\n+\txpcs_write(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_CTRL), val);\n+\n+\t/* 1.7 Assert tx_reset and rx_reset*/\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0);\n+\tval |= PMA_TX_GENCTRL0_TX_RST_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1);\n+\tval |= PMA_RX_GENCTRL1_RX_RST_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val);\n+\n+\t/* 1.8 Wait for more than 1us */\n+\tudelay(5);\n+\n+\t/* 1.9 Deassert tx_reset and rx_reset*/\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0);\n+\tval &= ~PMA_TX_GENCTRL0_TX_RST_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1);\n+\tval &= ~PMA_RX_GENCTRL1_RX_RST_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val);\n+\n+\t/* 1.10 Power down MPLLA */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL);\n+\tval = u16_replace_bits(val, 3, PMA_POWER_STATE_CTRL_TX0_PSTATE_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_POWER_STATE_CTRL, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL);\n+\tval &= ~PMA_MPLL_CMN_CTRL_MPLL_EN_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0);\n+\tval &= ~PMA_TX_GENCTRL0_TX_DT_EN_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL0, val);\n+\n+\t/* 1.11 Change RX0 power state to P2 */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0);\n+\tval &= ~PMA_RX_GENCTRL0_RX_DT_EN_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0, val);\n+\n+\t/* TODO: check if it is needed */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL);\n+\tval = u16_replace_bits(val, 1, PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL);\n+\tval = u16_replace_bits(val, 3, PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val);\n+\n+\t/* 1.12 Assert request of transmit and receive */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);\n+\tval |= PMA_TX_GENCTRL2_TX_REQ_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);\n+\tval |= PMA_RX_GENCTRL2_RX_REQ_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val);\n+\n+\t/* 1.13 Poll for acknlowledge */\n+\tbegin = get_timer(0);\n+\tdo {\n+\t\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);\n+\t\tif (get_timer(begin) > 500) {\n+\t\t\tdev_err(dev, \"Polling timeout, line: %d\\n\", __LINE__);\n+\t\t\tgoto timeout;\n+\t\t}\n+\t\tmdelay(10);\n+\t} while (val & PMA_TX_GENCTRL2_TX_REQ_0);\n+\n+\tbegin = get_timer(0);\n+\tdo {\n+\t\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);\n+\t\tif (get_timer(begin) > 500) {\n+\t\t\tdev_err(dev, \"Polling timeout, line: %d\\n\", __LINE__);\n+\t\t\tgoto timeout;\n+\t\t}\n+\t\tmdelay(10);\n+\t} while (val & PMA_RX_GENCTRL2_RX_REQ_0);\n+\n+\t/* 2 Config MPLL for 10G XGMII */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL);\n+\tval = u16_replace_bits(val, 6, PMA_REF_CLK_CTRL_REF_RANGE_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL);\n+\tval &= ~PMA_REF_CLK_CTRL_REF_CLK_DIV2;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL);\n+\tval |= PMA_REF_CLK_CTRL_REF_MPLLA_DIV2;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_REF_CLK_CTRL, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);\n+\tval &= ~PMA_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);\n+\tval |= PMA_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);\n+\tval |= PMA_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);\n+\tval &= ~PMA_MPLLA_CTRL2_MPLLA_TX_CLK_DIV_MASK;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);\n+\tval |= PMA_MPLLA_CTRL2_MPLLA_DIV_CLK_EN;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);\n+\tval = u16_replace_bits(val, 5, PMA_MPLLA_CTRL2_MPLLA_DIV_MULT_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_MPLLA_CTRL1);\n+\tval &= ~PMA_MPLLA_CTRL1_MPLLA_SSC_EN;\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL1, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_MPLLA_CTRL1);\n+\tval &= ~PMA_MPLLA_CTRL1_MPLLA_SSC_CLK_SEL;\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL1, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_MPLLA_CTRL5);\n+\tval &= ~PMA_MPLLA_CTRL5_MPLLA_SSC_FRQ_CNT_PK_MASK;\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL5, val);\n+\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL4, 0);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_MPLLA_CTRL5);\n+\tval &= ~PMA_MPLLA_CTRL5_MPLLA_SSC_SPD_EN;\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL5, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_MPLLA_CTRL1);\n+\tval &= ~PMA_MPLLA_CTRL1_MPLLA_FRACN_CTRL_MASK;\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL1, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL0);\n+\tval = u16_replace_bits(val, 33, PMA_MPLLA_CTRL0_MPLLA_MULTIPLIER_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL0, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1);\n+\tval = u16_replace_bits(val, 5, PMA_TX_GENCTRL1_VBOOST_LVL_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1, val);\n+\n+\tval = PMA_MPLLA_CTRL3_MPLLA_BANDWIDTH(0xA016);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL3, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MISC_CTRL0);\n+\tval = u16_replace_bits(val, 0x11, PMA_MISC_CTRL0_RX_VREF_CTRL_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_MISC_CTRL0, val);\n+\n+\tval = PMA_MISC_CTRL2_SUP_MISC(1);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_MISC_CTRL2, val);\n+\n+\tval = PMA_VCO_CAL_REF0_VCO_REF_LD_0(0x29);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_VCO_CAL_REF0, val);\n+\n+\tval = PMA_VCO_CAL_LD0_VCO_LD_VAL_0(0x549);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_VCO_CAL_LD0, val);\n+\n+\tval = PMA_RX_PPM_CTRL0_RX0_CDR_PPM_MAX(0x12);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_PPM_CTRL0, val);\n+\n+\t/* 3 Configure LANE0 for 10G XGMII */\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_TX_MISC_CTRL0, 0x0);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_RATE_CTRL, 0x0);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL);\n+\tval &= ~PMA_MPLL_CMN_CTRL_MPLLB_SEL_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_MPLL_CMN_CTRL, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);\n+\tval = u16_replace_bits(val, 3, PMA_TX_GENCTRL2_TX0_WIDTH_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1);\n+\tval |= PMA_TX_GENCTRL1_VBOOST_EN_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1, val);\n+\n+\tval = PMA_TX_BOOST_CTRL_TX0_IBOOST(0xf);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_BOOST_CTRL, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_EQ_CTRL0);\n+\tval = u16_replace_bits(val, 0, PMA_TX_EQ_CTRL0_TX_EQ_PRE_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_EQ_CTRL0, val);\n+\n+\tval = PMA_TX_EQ_CTRL1_TX_EQ_POST(0x20);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_EQ_CTRL1, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_EQ_CTRL0);\n+\tval = u16_replace_bits(val, 0x20, PMA_TX_EQ_CTRL0_TX_EQ_MAIN_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_EQ_CTRL0, val);\n+\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_RATE_CTRL, 0x0);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0);\n+\tval = u16_replace_bits(val, 0x2, PMA_RX_EQ_CTRL0_CTLE_POLE_0_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0);\n+\tval = u16_replace_bits(val, 0x10, PMA_RX_EQ_CTRL0_CTLE_BOOST_0_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL3);\n+\tval = u16_replace_bits(val, 0x7, PMA_RX_GENCTRL3_LOS_TRSHLD_0_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL3, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1);\n+\tval |= PMA_RX_CDR_CTRL1_VCO_STEP_CTRL_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1);\n+\tval |= PMA_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val);\n+\n+\tval = PMA_RX_MISC_CTRL0_RX0_MISC(0x12);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_MISC_CTRL0, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);\n+\tval = u16_replace_bits(val, 0x3, PMA_RX_GENCTRL2_RX0_WIDTH_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1);\n+\tval |= PMA_RX_GENCTRL1_RX_DIV16P5_CLK_EN_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val);\n+\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_CDR_CTRL, 0x0);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL3);\n+\tval &= ~PMA_RX_GENCTRL3_LOS_LFPS_EN_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL3, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_GENCTRL4);\n+\tval &= ~PMA_RX_GENCTRL4_RX_DFE_BYP_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_GENCTRL4, val);\n+\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_ATTN_CTRL, 0x0);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0);\n+\tval = u16_replace_bits(val, 0x5, PMA_RX_EQ_CTRL0_VGA1_GAIN_0_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0);\n+\tval = u16_replace_bits(val, 0x5, PMA_RX_EQ_CTRL0_VGA2_GAIN_0_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0, val);\n+\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_DFE_TAP_CTRL0, 0x0);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1);\n+\tval = u16_replace_bits(val, 0x1, PMA_RX_CDR_CTRL1_VCO_FRQBAND_0_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1);\n+\tval |= PMA_RX_GENCTRL1_RX_TERM_ACDC_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_IQ_CTRL0);\n+\tval = u16_replace_bits(val, 0x0, PMA_RX_IQ_CTRL0_RX0_DELTA_IQ_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_IQ_CTRL0, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5);\n+\tval &= ~PMA_RX_EQ_CTRL5_RX_ADPT_SEL_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5);\n+\tval = u16_replace_bits(val, 0x3, PMA_RX_EQ_CTRL5_RX0_ADPT_MODE_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5, val);\n+\n+\t/* 4 Configure XPCS for 10G XGMII */\n+\txpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_CTRL2), 0x0);\n+\n+\tval = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DIG_CTRL1));\n+\tval |= PCS_DIG_CTRL1_USXG_EN;\n+\txpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DIG_CTRL1), val);\n+\n+\tval = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_KR_CTRL1));\n+\tval = u16_replace_bits(val, 0x0, PCS_KR_CTRL1_USXG_MODE_MASK);\n+\txpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_KR_CTRL1), val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL0);\n+\tval = u16_replace_bits(val, 0x21, PMA_MPLLA_CTRL0_MPLLA_MULTIPLIER_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL0, val);\n+\n+\tval = PMA_MPLLA_CTRL3_MPLLA_BANDWIDTH(0xA016);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_MPLLA_CTRL3, val);\n+\n+\tval = PMA_VCO_CAL_LD0_VCO_LD_VAL_0(0x549);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_VCO_CAL_LD0, val);\n+\n+\tval = PMA_VCO_CAL_REF0_VCO_REF_LD_0(0x29);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_VCO_CAL_REF0, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4);\n+\tval |= PMA_RX_EQ_CTRL4_CONT_ADAPT_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4, val);\n+\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_RATE_CTRL, 0x0);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_RATE_CTRL, 0x0);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2);\n+\tval = u16_replace_bits(val, 0x3, PMA_TX_GENCTRL2_TX0_WIDTH_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_TX_GENCTRL2, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);\n+\tval = u16_replace_bits(val, 0x3, PMA_RX_GENCTRL2_RX0_WIDTH_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);\n+\tval |= PMA_MPLLA_CTRL2_MPLLA_DIV16P5_CLK_EN;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);\n+\tval |= PMA_MPLLA_CTRL2_MPLLA_DIV10_CLK_EN;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2);\n+\tval &= ~PMA_MPLLA_CTRL2_MPLLA_DIV8_CLK_EN;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_MPLLA_CTRL2, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1);\n+\tval |= PMA_TX_GENCTRL1_VBOOST_EN_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0);\n+\tval = u16_replace_bits(val, 0x10, PMA_RX_EQ_CTRL0_CTLE_BOOST_0_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL0, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1);\n+\tval |= PMA_RX_CDR_CTRL1_VCO_STEP_CTRL_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1);\n+\tval |= PMA_RX_CDR_CTRL1_VCO_TEMP_COMP_EN_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val);\n+\n+\tval = PMA_RX_MISC_CTRL0_RX0_MISC(0x12);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_MISC_CTRL0, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_GENCTRL4);\n+\tval &= ~PMA_RX_GENCTRL4_RX_DFE_BYP_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_GENCTRL4, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_RX_CDR_CTRL1);\n+\tval = u16_replace_bits(val, 0x1, PMA_RX_CDR_CTRL1_VCO_FRQBAND_0_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_RX_CDR_CTRL1, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_IQ_CTRL0);\n+\tval = u16_replace_bits(val, 0x0, PMA_RX_IQ_CTRL0_RX0_DELTA_IQ_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_IQ_CTRL0, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5);\n+\tval = u16_replace_bits(val, 0x3, PMA_RX_EQ_CTRL5_RX0_ADPT_MODE_MASK);\n+\txpcs_phy_write_pma(dev, PMA_MP_16G_25G_RX_EQ_CTRL5, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1);\n+\tval &= ~PMA_TX_GENCTRL1_TX_CLK_RDY_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1, val);\n+\n+\t/* 5 Assert soft reset */\n+\tval = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DIG_CTRL1));\n+\tval |= PCS_DIG_CTRL1_VR_RST;\n+\txpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DIG_CTRL1), val);\n+\n+\t/* 6 Poll for SRAM initialization done */\n+\tbegin = get_timer(0);\n+\tdo {\n+\t\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_SRAM);\n+\t\tif (get_timer(begin) > 500) {\n+\t\t\tdev_err(dev, \"Polling timeout, line: %d\\n\", __LINE__);\n+\t\t\tgoto timeout;\n+\t\t}\n+\t\tmdelay(10);\n+\t} while (!(val & PMA_SRAM_INIT_DN));\n+\n+\t/* 7 Assert SRAM external loading done */\n+\t/* Workaround */\n+\t// xpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_SRAM, PMA_SRAM_EXT_LD_DN);\n+\txpcs_phy_write(dev, XPCS_PHY_GLOBAL, XPCS_PHY_REG(GLOBAL_CTRL_EX_0), GLOBAL_CTRL_EX_0_PHY_SRAM_BYPASS);\n+\n+\t/* 8 Poll for vendor-specific soft reset */\n+\tbegin = get_timer(0);\n+\tdo {\n+\t\tval = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DIG_CTRL1));\n+\t\tif (get_timer(begin) > 500) {\n+\t\t\tdev_err(dev, \"Polling timeout, line: %d\\n\", __LINE__);\n+\t\t\tgoto timeout;\n+\t\t}\n+\t\tmdelay(10);\n+\t} while (val & PCS_DIG_CTRL1_VR_RST);\n+\n+\t/* 9 Turn receive to P0 state */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1);\n+\tval &= ~PMA_RX_GENCTRL1_RX_RST_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL1, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL);\n+\tval &= ~PMA_RX_POWER_STATE_CTRL_RX_DISABLE_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val);\n+\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL);\n+\tval &= ~PMA_RX_POWER_STATE_CTRL_RX0_PSTATE_MASK;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_POWER_STATE_CTRL, val);\n+\n+\t/* 10 Enable receiver data output from PHY */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0);\n+\tval |= PMA_RX_GENCTRL0_RX_DT_EN_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_GENCTRL0, val);\n+\n+\t/* 11 Assert request of receive */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);\n+\tval |= PMA_RX_GENCTRL2_RX_REQ_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2, val);\n+\n+\t/* 11.1 Poll for acknowledge */\n+\tbegin = get_timer(0);\n+\tdo {\n+\t\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_RX_GENCTRL2);\n+\t\tif (get_timer(begin) > 500) {\n+\t\t\tdev_err(dev, \"Polling timeout, line: %d\\n\", __LINE__);\n+\t\t\tgoto timeout;\n+\t\t}\n+\t\tmdelay(10);\n+\t} while (val & PMA_RX_GENCTRL2_RX_REQ_0);\n+\n+\t/* 12 Assert TX0 clock is active and stable */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1);\n+\tval |= PMA_TX_GENCTRL1_TX_CLK_RDY_0;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_TX_GENCTRL1, val);\n+\n+\t/*\n+\t * 13.1 Configure XPCS to consider Loss-of-Signal indicated by the\n+\t * PHY while evaluating the receive link status\n+\t */\n+\tval = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL));\n+\tval |= PCS_DEBUG_CTRL_SUPRESS_LOS_DET;\n+\txpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL), val);\n+\t/*\n+\t * 13.2 Configure XPCS to deassert \"receiver data enable\" on\n+\t * detecting of Loss-of-Signal\n+\t */\n+\tval = xpcs_read(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL));\n+\tval |= PCS_DEBUG_CTRL_RX_DT_EN_CTL;\n+\txpcs_write(dev, MDIO_MMD_PCS, XPCS_PHY_REG(PCS_DEBUG_CTRL), val);\n+\n+\t/* 14 Poll for DPLL lock status for Lane 0 */\n+\tbegin = get_timer(0);\n+\tdo {\n+\t\tval = xpcs_phy_read_pma(dev, PMA_RX_LSTS);\n+\t\tif (get_timer(begin) > 500) {\n+\t\t\tdev_err(dev, \"Polling timeout, line: %d\\n\", __LINE__);\n+\t\t\tgoto timeout;\n+\t\t}\n+\t\tmdelay(10);\n+\t} while (!(val & PMA_RX_LSTS_RX_VALID_0));\n+\n+\t/* 15 Assert request of receive adaptation */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4);\n+\tval |= PMA_RX_EQ_CTRL4_RX_AD_REQ;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4, val);\n+\n+\t/* 16 Poll for acknowledge */\n+\tbegin = get_timer(0);\n+\tdo {\n+\t\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_MISC_STS);\n+\t\tif (get_timer(begin) > 500) {\n+\t\t\tdev_err(dev, \"Polling timeout, line: %d\\n\", __LINE__);\n+\t\t\tgoto timeout;\n+\t\t}\n+\t\tmdelay(10);\n+\t} while (!(val & PMA_MISC_STS_RX_ADPT_ACK));\n+\n+\t/* 17 Deassert request of receive adaptation */\n+\tval = xpcs_phy_read_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4);\n+\tval &= ~PMA_RX_EQ_CTRL4_RX_AD_REQ;\n+\txpcs_phy_write_pma(dev, PMA_MP_12G_16G_25G_RX_EQ_CTRL4, val);\n+\n+\t/* 18 Set the value of Config_Reg to 0 for Clause 37 autonegotiation. */\n+\tval = xpcs_read(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_AN_CTRL));\n+\tval &= ~MII_AN_CTRL_TX_CONFIG;\n+\txpcs_write(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_AN_CTRL), val);\n+\n+\t/* 19 Select XGMII speed */\n+\tval = xpcs_read(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_CTRL));\n+\tval &= ~MII_CTRL_SS5;\n+\tval |= MII_CTRL_SS6 | MII_CTRL_SS13;\n+\txpcs_write(dev, MDIO_MMD_VEND2, XPCS_PHY_REG(MII_CTRL), val);\n+\n+\tval = xpcs_phy_usxgmii_init_seq_2(dev);\n+\tif (val)\n+\t\treturn val;\n+\n+\treturn 0;\n+\n+timeout:\n+\treturn -ETIMEDOUT;\n+}\n+\n+u32 xpcs_phy_get_id(struct udevice *dev)\n+{\n+\tint ret;\n+\tu32 id;\n+\n+\t/* First, search C73 PCS using PCS MMD */\n+\tret = xpcs_phy_read(dev, XPCS_PHY_GLOBAL, XPCS_PHY_REG(IDCODE_HI));\n+\tif (ret < 0)\n+\t\treturn 0xffffffff;\n+\n+\tid = ret << 16;\n+\n+\tret = xpcs_phy_read(dev, XPCS_PHY_GLOBAL, XPCS_PHY_REG(IDCODE_LO));\n+\tif (ret < 0)\n+\t\treturn 0xffffffff;\n+\n+\t/* If Device IDs are not all zeros or all ones,\n+\t * we found C73 AN-type device\n+\t */\n+\tif ((id | ret) && (id | ret) != 0xffffffff)\n+\t\treturn id | ret;\n+\n+\treturn 0xffffffff;\n+}\n","prefixes":["v1","2/2"]}