{"id":2223395,"url":"http://patchwork.ozlabs.org/api/patches/2223395/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260415-pcie-intel-gw-v4-4-ad45d2418c8e@dev.tdt.de/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415-pcie-intel-gw-v4-4-ad45d2418c8e@dev.tdt.de>","list_archive_url":null,"date":"2026-04-15T08:01:50","name":"[v4,4/7] PCI: intel-gw: Enable clock before phy init","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"06b764a98d01d546fbcc9e9d45361ce91302bb27","submitter":{"id":72238,"url":"http://patchwork.ozlabs.org/api/people/72238/?format=json","name":"Florian Eckert","email":"fe@dev.tdt.de"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260415-pcie-intel-gw-v4-4-ad45d2418c8e@dev.tdt.de/mbox/","series":[{"id":499942,"url":"http://patchwork.ozlabs.org/api/series/499942/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=499942","date":"2026-04-15T08:01:47","name":"PCI: intel-gw: Fixes to make the driver working again","version":4,"mbox":"http://patchwork.ozlabs.org/series/499942/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223395/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223395/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=temperror header.d=dev.tdt.de header.i=@dev.tdt.de header.a=rsa-sha256\n header.s=z1-selector1 header.b=uzt5RkTh;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"utf-8\"","Message-ID":"<20260415-pcie-intel-gw-v4-4-ad45d2418c8e@dev.tdt.de>","References":"<20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de>","In-Reply-To":"<20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de>","To":"Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= ,\n Manivannan Sadhasivam , Rob Herring ,\n Bjorn Helgaas , Johan Hovold ,\n Sajid Dalvi , Ajay Agarwal ,\n Krzysztof Kozlowski , Conor Dooley ","Cc":"linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org, Florian Eckert ,\n\tEckert.Florian@googlemail.com, ms@dev.tdt.de","X-Mailer":"b4 0.14.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1776240111; l=2721;\n i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id;\n bh=e2R433hJ5rO3HTn7PeimYHVCAsltELW5gkTR8+BYSdw=;\n b=jhTTvuH4kGGPcppcdUxMOsv396KZls8NkMVKLAn92E7cMkW5+WepgfPLavzZf+FYVVu+xhxjo\n ptJNh+mxsYkAy4g218lthbBadJw+Hs/jJvMLMG8Pf0zSJgpc2qPswyy","X-Developer-Key":"i=fe@dev.tdt.de; a=ed25519;\n pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk=","Content-Transfer-Encoding":"quoted-printable","X-purgate-ID":"151534::1776240115-54C8D2EC-2FD84FEA/0/0","X-purgate":"clean","X-purgate-type":"clean"},"content":"To ensure that the boot sequence is correct, the dwc pcie core clock must\nbe switched on before phy init call [1]. This changes are based on patched\nkernel sources of the MaxLinear SDK.\n\nThe reason why the MaxLinear SDK is used as a reference here is, that this\npcie dwc IP is used in the URX851 and URX850 SoC. This SoC was originally\ndeveloped by Intel when they acquired Lantiq’s home networking division in\n2015 [2]. In 2020 the home network division was sold to MaxLinear [3].\nSince then, this SoC belongs to MaxLinear. They use their own SDK,\nwhich runs on kernel version '5.15.x'.\n\n[1] https://github.com/maxlinear/linux/blob/updk_9.1.90/drivers/pci/controller/dwc/pcie-intel-gw.c#L544\n[2] https://www.intc.com/news-events/press-releases/detail/364/intel-to-acquire-lantiq-advancing-the-connected-home\n[3] https://investors.maxlinear.com/press-releases/detail/395/maxlinear-to-acquire-intels-home-gateway-platform\n\nSigned-off-by: Florian Eckert \n---\n drivers/pci/controller/dwc/pcie-intel-gw.c | 19 ++++++++++---------\n 1 file changed, 10 insertions(+), 9 deletions(-)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c\nindex e88b8243cc41c607c39e4d58c4dcd8c8c082e8b0..6d9499d954674a26a74bff56b7fb5759767424c0 100644\n--- a/drivers/pci/controller/dwc/pcie-intel-gw.c\n+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c\n@@ -291,13 +291,9 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)\n \n \tintel_pcie_core_rst_assert(pcie);\n \tintel_pcie_device_rst_assert(pcie);\n-\n-\tret = phy_init(pcie->phy);\n-\tif (ret)\n-\t\treturn ret;\n-\n \tintel_pcie_core_rst_deassert(pcie);\n \n+\t/* Controller clock must be provided earlier than PHY */\n \tret = clk_prepare_enable(pcie->core_clk);\n \tif (ret) {\n \t\tdev_err(pcie->pci.dev, \"Core clock enable failed: %d\\n\", ret);\n@@ -306,13 +302,17 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)\n \n \tpci->atu_base = pci->dbi_base + 0xC0000;\n \n+\tret = phy_init(pcie->phy);\n+\tif (ret)\n+\t\tgoto phy_err;\n+\n \tintel_pcie_ltssm_disable(pcie);\n \tintel_pcie_link_setup(pcie);\n \tintel_pcie_init_n_fts(pci);\n \n \tret = dw_pcie_setup_rc(&pci->pp);\n \tif (ret)\n-\t\tgoto app_init_err;\n+\t\tgoto err;\n \n \tdw_pcie_upconfig_setup(pci);\n \n@@ -321,17 +321,18 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)\n \n \tret = dw_pcie_wait_for_link(pci);\n \tif (ret)\n-\t\tgoto app_init_err;\n+\t\tgoto err;\n \n \tintel_pcie_core_irq_enable(pcie);\n \n \treturn 0;\n \n-app_init_err:\n+err:\n+\tphy_exit(pcie->phy);\n+phy_err:\n \tclk_disable_unprepare(pcie->core_clk);\n clk_err:\n \tintel_pcie_core_rst_assert(pcie);\n-\tphy_exit(pcie->phy);\n \n \treturn ret;\n }\n","prefixes":["v4","4/7"]}