{"id":2223394,"url":"http://patchwork.ozlabs.org/api/patches/2223394/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260415-pcie-intel-gw-v4-3-ad45d2418c8e@dev.tdt.de/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415-pcie-intel-gw-v4-3-ad45d2418c8e@dev.tdt.de>","list_archive_url":null,"date":"2026-04-15T08:01:49","name":"[v4,3/7] PCI: intel-gw: Move interrupt enable to own function","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6d9de3514c54a43a4ace14177a8656cd965eac4e","submitter":{"id":72238,"url":"http://patchwork.ozlabs.org/api/people/72238/?format=json","name":"Florian Eckert","email":"fe@dev.tdt.de"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260415-pcie-intel-gw-v4-3-ad45d2418c8e@dev.tdt.de/mbox/","series":[{"id":499942,"url":"http://patchwork.ozlabs.org/api/series/499942/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=499942","date":"2026-04-15T08:01:47","name":"PCI: intel-gw: Fixes to make the driver working again","version":4,"mbox":"http://patchwork.ozlabs.org/series/499942/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223394/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223394/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=temperror header.d=dev.tdt.de header.i=@dev.tdt.de header.a=rsa-sha256\n header.s=z1-selector1 header.b=lfCM565k;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"utf-8\"","Message-ID":"<20260415-pcie-intel-gw-v4-3-ad45d2418c8e@dev.tdt.de>","References":"<20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de>","In-Reply-To":"<20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de>","To":"Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= ,\n Manivannan Sadhasivam , Rob Herring ,\n Bjorn Helgaas , Johan Hovold ,\n Sajid Dalvi , Ajay Agarwal ,\n Krzysztof Kozlowski , Conor Dooley ","Cc":"linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org, Florian Eckert ,\n\tEckert.Florian@googlemail.com, ms@dev.tdt.de","X-Mailer":"b4 0.14.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1776240111; l=2926;\n i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id;\n bh=ZYKI9htHzLsLWQm9mMvJbP0KpPmuZ1vngPu0F8zCXMI=;\n b=jcsd9M7td+8J8ulKtrrL+BPo6v8bhL6aK4wA3oMZfabsnaPpY8ewS3sf0kgvOvqJNKS5qRymy\n awd53nP3yC4B3UgMH3YTeBpnIMkv7DXnkejsQQbwZQLswio7syQQSmF","X-Developer-Key":"i=fe@dev.tdt.de; a=ed25519;\n pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk=","Content-Transfer-Encoding":"quoted-printable","X-purgate-type":"clean","X-purgate":"clean","X-purgate-ID":"151534::1776240115-3DFF02EC-420E88E8/0/0"},"content":"To improve the readability of the code, move the interrupt enable\ninstructions to a separate function. That is already done for the disable\ninterrupt instruction.\n\nIn addition, all pending interrupts are cleared and disabled, just as this\nis done in the disable function 'intel_pcie_core_irq_disable()'. After\nthat, all relevant interrupts are enabled again. The 'PCIE_APP_IRNEN'\ndefinition contains all the relevant interrupts that are of interest.\n\nThis change is also done in the MaxLinear SDK [1]. As I unfortunately\ndon’t have any documentation for this IP core, I suspect that the\nintention is to set the IP core for interrupt handling to a specific\nstate. Perhaps the problem is that the IP core did not reinitialize the\ninterrupt register properly after a power cycle.\n\nIn my view, it can’t do any harm to switch the interrupt off and then on\nagain to set them to a specific state.\n\nThe reason why the MaxLinear SDK is used as a reference here is, that this\npcie dwc IP is used in the URX851 and URX850 SoC. This SoC was originally\ndeveloped by Intel when they acquired Lantiq’s home networking division in\n2015 [2]. In 2020 the home network division was sold to MaxLinear [3].\nSince then, this SoC belongs to MaxLinear. They use their own SDK,\nwhich runs on kernel version '5.15.x'.\n\n[1] https://github.com/maxlinear/linux/blob/updk_9.1.90/drivers/pci/controller/dwc/pcie-intel-gw.c#L431\n[2] https://www.intc.com/news-events/press-releases/detail/364/intel-to-acquire-lantiq-advancing-the-connected-home\n[3] https://investors.maxlinear.com/press-releases/detail/395/maxlinear-to-acquire-intels-home-gateway-platform\n\nSigned-off-by: Florian Eckert \n---\n drivers/pci/controller/dwc/pcie-intel-gw.c | 11 ++++++++---\n 1 file changed, 8 insertions(+), 3 deletions(-)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c\nindex 80d1607c46cbbb1e274b37a0bb9377a877678f5d..e88b8243cc41c607c39e4d58c4dcd8c8c082e8b0 100644\n--- a/drivers/pci/controller/dwc/pcie-intel-gw.c\n+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c\n@@ -195,6 +195,13 @@ static void intel_pcie_device_rst_deassert(struct intel_pcie *pcie)\n \tgpiod_set_value_cansleep(pcie->reset_gpio, 0);\n }\n \n+static void intel_pcie_core_irq_enable(struct intel_pcie *pcie)\n+{\n+\tpcie_app_wr(pcie, PCIE_APP_IRNEN, 0);\n+\tpcie_app_wr(pcie, PCIE_APP_IRNCR, PCIE_APP_IRN_INT);\n+\tpcie_app_wr(pcie, PCIE_APP_IRNEN, PCIE_APP_IRN_INT);\n+}\n+\n static void intel_pcie_core_irq_disable(struct intel_pcie *pcie)\n {\n \tpcie_app_wr(pcie, PCIE_APP_IRNEN, 0);\n@@ -316,9 +323,7 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)\n \tif (ret)\n \t\tgoto app_init_err;\n \n-\t/* Enable integrated interrupts */\n-\tpcie_app_wr_mask(pcie, PCIE_APP_IRNEN, PCIE_APP_IRN_INT,\n-\t\t\t PCIE_APP_IRN_INT);\n+\tintel_pcie_core_irq_enable(pcie);\n \n \treturn 0;\n \n","prefixes":["v4","3/7"]}