{"id":2223373,"url":"http://patchwork.ozlabs.org/api/patches/2223373/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260415-ultrarisc-pcie-v3-1-73f06e972616@ultrarisc.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415-ultrarisc-pcie-v3-1-73f06e972616@ultrarisc.com>","list_archive_url":null,"date":"2026-04-15T07:21:17","name":"[v3,1/3] riscv: add UltraRISC SoC family Kconfig support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"94a8dda831c7b228dbc6f163f6a8b9b50b731975","submitter":{"id":92886,"url":"http://patchwork.ozlabs.org/api/people/92886/?format=json","name":"Jia Wang","email":"wangjia@ultrarisc.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260415-ultrarisc-pcie-v3-1-73f06e972616@ultrarisc.com/mbox/","series":[{"id":499935,"url":"http://patchwork.ozlabs.org/api/series/499935/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=499935","date":"2026-04-15T07:21:17","name":"riscv: Add PCIe support for UltraRISC DP1000 SoC","version":3,"mbox":"http://patchwork.ozlabs.org/series/499935/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223373/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223373/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ultrarisc.com header.i=@ultrarisc.com\n header.a=rsa-sha256 header.s=dkim header.b=UD9mmmKm;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260415-ultrarisc-pcie-v3-1-73f06e972616@ultrarisc.com>","References":"<20260415-ultrarisc-pcie-v3-0-73f06e972616@ultrarisc.com>","In-Reply-To":"<20260415-ultrarisc-pcie-v3-0-73f06e972616@ultrarisc.com>","To":"Paul Walmsley , Palmer Dabbelt ,\n Albert Ou , Alexandre Ghiti ,\n Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= ,\n Manivannan Sadhasivam , Rob Herring ,\n Bjorn Helgaas , Jingoo Han ,\n Xincheng Zhang ,\n Krzysztof Kozlowski ,\n Conor Dooley ","Cc":"linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,\n linux-pci@vger.kernel.org, devicetree@vger.kernel.org,\n Jia Wang ","X-Mailer":"b4 0.15-dev","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1776237679; l=758;\n i=wangjia@ultrarisc.com; s=20260309; h=from:subject:message-id;\n bh=Zl1FrIKf17blskhbPmYq7tClMDdF35LMCald+AmIzEY=;\n b=v0urUIZhmDHLcJS8l8hylWgWBx7DszuDyaecCFxXIGZ6mVxW7+E/46bwLHk1u35PH3Re4Nu6M\n nEXFzy8jO5KConmUiFmr1qOiBjw8zKh+HGYFVpQsayt9kaX9OX42VHg","X-Developer-Key":"i=wangjia@ultrarisc.com; a=ed25519;\n pk=XvYkrelqJIIzobY7j+nIg8rsfv5kzaOzuc1UPhd087U=","X-CM-TRANSID":"AQAAfwAnYUKdPN9poSgCAA--.1324S3","X-Coremail-Antispam":"1UD129KBjvdXoW7Jw45XFy3Xry8GFWDXw4Dtwb_yoW3GFg_G3\n\t4xJ348uFyrAFW8uFZ8Wrs3WFyrAws8WFy5Gr1ftryDu34xXw1xW3yDKF10yw1Uuw15Xa1k\n\tXrWfAr4fAry3tjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT\n\t9fnUUIcSsGvfJTRUUUbQAYjsxI4VWxJwAYFVCjjxCrM7AC8VAFwI0_Wr0E3s1l1xkIjI8I\n\t6I8E6xAIw20EY4v20xvaj40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7\n\tIE14v26r18M28IrcIa0xkI8VCY1x0267AKxVW8JVW5JwA2ocxC64kIII0Yj41l84x0c7CE\n\tw4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6x\n\tkF7I0E14v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr0_Cr1l84ACjcxK6I8E87Iv6xkF\n\t7I0E14v26r4j6r4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4\n\txG6I80ewAv7VC0I7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCa\n\tFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI4\n\t02YVCY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY02Avz4vE-syl42xK82IY\n\tc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s\n\t026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF\n\t0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0x\n\tvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv\n\t6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjTRIoGLUUUUU","X-CM-SenderInfo":"pzdqwylld63zxwud2x1vfou0bp/1tbiAQASEWnfCz0AFAAAsW"},"content":"The first SoC in the UltraRISC series is UR-DP1000, containing octa\nUltraRISC CP100 cores.\n\nSigned-off-by: Jia Wang \n---\n arch/riscv/Kconfig.socs | 6 ++++++\n 1 file changed, 6 insertions(+)","diff":"diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs\nindex d621b85dd63b..0b4d06a7b4bf 100644\n--- a/arch/riscv/Kconfig.socs\n+++ b/arch/riscv/Kconfig.socs\n@@ -84,6 +84,12 @@ config ARCH_THEAD\n \thelp\n \t This enables support for the RISC-V based T-HEAD SoCs.\n \n+config ARCH_ULTRARISC\n+\tbool \"UltraRISC RISC-V SoCs\"\n+\thelp\n+\t This enables support for UltraRISC SoC platform hardware,\n+\t including boards based on the UR-DP1000.\n+\n config ARCH_VIRT\n \tbool \"QEMU Virt Machine\"\n \tselect POWER_RESET\n","prefixes":["v3","1/3"]}