{"id":2223368,"url":"http://patchwork.ozlabs.org/api/patches/2223368/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415064838.652297-3-joel@jms.id.au/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260415064838.652297-3-joel@jms.id.au>","list_archive_url":null,"date":"2026-04-15T06:48:34","name":"[v2,2/4] hw/riscv/boot: Account for discontiguous memory when loading firmware","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6c7d464e8f86a01450ac15a22d27b6b415550876","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/people/48628/?format=json","name":"Joel Stanley","email":"joel@jms.id.au"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260415064838.652297-3-joel@jms.id.au/mbox/","series":[{"id":499931,"url":"http://patchwork.ozlabs.org/api/series/499931/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499931","date":"2026-04-15T06:48:32","name":"hw/riscv: Boot setup improvements","version":2,"mbox":"http://patchwork.ozlabs.org/series/499931/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223368/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223368/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=aUT3+fWw;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwWwk3PQNz1yDF\n\tfor ; Wed, 15 Apr 2026 16:49:58 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wCu3f-0001Lj-HR; Wed, 15 Apr 2026 02:49:07 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wCu3Z-0001L7-JA\n for qemu-devel@nongnu.org; Wed, 15 Apr 2026 02:49:01 -0400","from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wCu3X-0001jD-J8\n for qemu-devel@nongnu.org; Wed, 15 Apr 2026 02:49:01 -0400","by mail-pl1-x62c.google.com with SMTP id\n d9443c01a7336-2b458ca2296so21993605ad.0\n for ; Tue, 14 Apr 2026 23:48:59 -0700 (PDT)","from donnager-debian.. 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Srinivasan , qemu-riscv@nongnu.org","Subject":"[PATCH v2 2/4] hw/riscv/boot: Account for discontiguous memory when\n loading firmware","Date":"Wed, 15 Apr 2026 16:48:34 +1000","Message-ID":"<20260415064838.652297-3-joel@jms.id.au>","X-Mailer":"git-send-email 2.47.3","In-Reply-To":"<20260415064838.652297-1-joel@jms.id.au>","References":"<20260415064838.652297-1-joel@jms.id.au>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::62c;\n envelope-from=joel.stan@gmail.com; helo=mail-pl1-x62c.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001,\n FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Nicholas Piggin \n\nThis loads firmware into the first (low) memory range,\naccounting for machines having discontiguous memory regions.\n\nSigned-off-by: Nicholas Piggin \nReviewed-by: Daniel Henrique Barboza \nSigned-off-by: Joel Stanley \n---\n include/hw/riscv/boot.h | 5 ++++-\n hw/riscv/boot.c | 18 ++++++++++++------\n hw/riscv/microchip_pfsoc.c | 6 ++++--\n hw/riscv/opentitan.c | 6 ++++--\n hw/riscv/shakti_c.c | 6 +++++-\n hw/riscv/sifive_u.c | 3 ++-\n hw/riscv/spike.c | 6 ++++--\n hw/riscv/virt.c | 7 ++++---\n hw/riscv/xiangshan_kmh.c | 6 +++++-\n 9 files changed, 44 insertions(+), 19 deletions(-)","diff":"diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h\nindex 115e3222174f..fb90bf12399e 100644\n--- a/include/hw/riscv/boot.h\n+++ b/include/hw/riscv/boot.h\n@@ -53,13 +53,16 @@ void riscv_boot_info_init_discontig_mem(RISCVBootInfo *info,\n vaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,\n hwaddr firmware_end_addr);\n hwaddr riscv_find_and_load_firmware(MachineState *machine,\n+ RISCVBootInfo *info,\n const char *default_machine_firmware,\n hwaddr *firmware_load_addr,\n symbol_fn_t sym_cb);\n const char *riscv_default_firmware_name(RISCVHartArrayState *harts);\n char *riscv_find_firmware(const char *firmware_filename,\n const char *default_machine_firmware);\n-hwaddr riscv_load_firmware(const char *firmware_filename,\n+hwaddr riscv_load_firmware(MachineState *machine,\n+ RISCVBootInfo *info,\n+ const char *firmware_filename,\n hwaddr *firmware_load_addr,\n symbol_fn_t sym_cb);\n void riscv_load_kernel(MachineState *machine,\ndiff --git a/hw/riscv/boot.c b/hw/riscv/boot.c\nindex 9babb85b0458..f3857e984240 100644\n--- a/hw/riscv/boot.c\n+++ b/hw/riscv/boot.c\n@@ -145,6 +145,7 @@ char *riscv_find_firmware(const char *firmware_filename,\n }\n \n hwaddr riscv_find_and_load_firmware(MachineState *machine,\n+ RISCVBootInfo *info,\n const char *default_machine_firmware,\n hwaddr *firmware_load_addr,\n symbol_fn_t sym_cb)\n@@ -157,7 +158,8 @@ hwaddr riscv_find_and_load_firmware(MachineState *machine,\n \n if (firmware_filename) {\n /* If not \"none\" load the firmware */\n- firmware_end_addr = riscv_load_firmware(firmware_filename,\n+ firmware_end_addr = riscv_load_firmware(machine, info,\n+ firmware_filename,\n firmware_load_addr, sym_cb);\n g_free(firmware_filename);\n }\n@@ -165,10 +167,13 @@ hwaddr riscv_find_and_load_firmware(MachineState *machine,\n return firmware_end_addr;\n }\n \n-hwaddr riscv_load_firmware(const char *firmware_filename,\n+hwaddr riscv_load_firmware(MachineState *machine,\n+ RISCVBootInfo *info,\n+ const char *firmware_filename,\n hwaddr *firmware_load_addr,\n symbol_fn_t sym_cb)\n {\n+ uint64_t mem_size = info->ram_low_size ?: machine->ram_size;\n uint64_t firmware_entry, firmware_end;\n ssize_t firmware_size;\n \n@@ -183,7 +188,7 @@ hwaddr riscv_load_firmware(const char *firmware_filename,\n \n firmware_size = load_image_targphys_as(firmware_filename,\n *firmware_load_addr,\n- current_machine->ram_size, NULL,\n+ mem_size, NULL,\n NULL);\n \n if (firmware_size > 0) {\n@@ -197,7 +202,7 @@ hwaddr riscv_load_firmware(const char *firmware_filename,\n static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info)\n {\n const char *filename = machine->initrd_filename;\n- uint64_t mem_size = machine->ram_size;\n+ uint64_t mem_size = info->ram_low_size ?: machine->ram_size;\n void *fdt = machine->fdt;\n hwaddr start, end;\n ssize_t size;\n@@ -243,6 +248,7 @@ void riscv_load_kernel(MachineState *machine,\n bool load_initrd,\n symbol_fn_t sym_cb)\n {\n+ uint64_t mem_size = info->ram_low_size ?: machine->ram_size;\n const char *kernel_filename = machine->kernel_filename;\n ssize_t kernel_size;\n void *fdt = machine->fdt;\n@@ -274,7 +280,7 @@ void riscv_load_kernel(MachineState *machine,\n }\n \n kernel_size = load_image_targphys_as(kernel_filename, kernel_start_addr,\n- current_machine->ram_size, NULL, NULL);\n+ mem_size, NULL, NULL);\n if (kernel_size > 0) {\n info->kernel_size = kernel_size;\n info->image_low_addr = kernel_start_addr;\n@@ -370,7 +376,7 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,\n dtb_start = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);\n \n if (dtb_start_limit && (dtb_start < dtb_start_limit)) {\n- error_report(\"No enough memory to place DTB after kernel/initrd\");\n+ error_report(\"Not enough memory to place DTB after kernel/initrd\");\n exit(1);\n }\n \ndiff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c\nindex 743f31f00578..1d1ddb05a882 100644\n--- a/hw/riscv/microchip_pfsoc.c\n+++ b/hw/riscv/microchip_pfsoc.c\n@@ -618,18 +618,20 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)\n firmware_load_addr = RESET_VECTOR;\n }\n \n+ riscv_boot_info_init(&boot_info, &s->soc.u_cpus);\n+\n /* Load the firmware if necessary */\n firmware_end_addr = firmware_load_addr;\n if (firmware_name) {\n char *filename = riscv_find_firmware(firmware_name, NULL);\n if (filename) {\n- firmware_end_addr = riscv_load_firmware(filename,\n+ firmware_end_addr = riscv_load_firmware(machine, &boot_info,\n+ filename,\n &firmware_load_addr, NULL);\n g_free(filename);\n }\n }\n \n- riscv_boot_info_init(&boot_info, &s->soc.u_cpus);\n if (machine->kernel_filename) {\n kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,\n firmware_end_addr);\ndiff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c\nindex 309125e854bc..8cd660dd4154 100644\n--- a/hw/riscv/opentitan.c\n+++ b/hw/riscv/opentitan.c\n@@ -99,12 +99,14 @@ static void opentitan_machine_init(MachineState *machine)\n memory_region_add_subregion(sys_mem,\n memmap[IBEX_DEV_RAM].base, machine->ram);\n \n+ riscv_boot_info_init(&boot_info, &s->soc.cpus);\n+\n if (machine->firmware) {\n hwaddr firmware_load_addr = memmap[IBEX_DEV_RAM].base;\n- riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL);\n+ riscv_load_firmware(machine, &boot_info, machine->firmware,\n+ &firmware_load_addr, NULL);\n }\n \n- riscv_boot_info_init(&boot_info, &s->soc.cpus);\n if (machine->kernel_filename) {\n riscv_load_kernel(machine, &boot_info,\n memmap[IBEX_DEV_RAM].base,\ndiff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c\nindex 49a39b30212d..eb720d9cdf5d 100644\n--- a/hw/riscv/shakti_c.c\n+++ b/hw/riscv/shakti_c.c\n@@ -45,6 +45,7 @@ static void shakti_c_machine_state_init(MachineState *mstate)\n {\n ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);\n MemoryRegion *system_memory = get_system_memory();\n+ RISCVBootInfo boot_info;\n hwaddr firmware_load_addr = shakti_c_memmap[SHAKTI_C_RAM].base;\n \n /* Initialize SoC */\n@@ -57,8 +58,11 @@ static void shakti_c_machine_state_init(MachineState *mstate)\n shakti_c_memmap[SHAKTI_C_RAM].base,\n mstate->ram);\n \n+ riscv_boot_info_init(&boot_info, &sms->soc.cpus);\n+\n if (mstate->firmware) {\n- riscv_load_firmware(mstate->firmware, &firmware_load_addr, NULL);\n+ riscv_load_firmware(mstate, &boot_info, mstate->firmware,\n+ &firmware_load_addr, NULL);\n }\n \n /* ROM reset vector */\ndiff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c\nindex 7ec67b256514..4c526f73edf6 100644\n--- a/hw/riscv/sifive_u.c\n+++ b/hw/riscv/sifive_u.c\n@@ -590,7 +590,8 @@ static void sifive_u_machine_init(MachineState *machine)\n }\n \n firmware_name = riscv_default_firmware_name(&s->soc.u_cpus);\n- firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,\n+ firmware_end_addr = riscv_find_and_load_firmware(machine, &boot_info,\n+ firmware_name,\n &start_addr, NULL);\n \n riscv_boot_info_init(&boot_info, &s->soc.u_cpus);\ndiff --git a/hw/riscv/spike.c b/hw/riscv/spike.c\nindex 35c696f891d8..6ee915a8ba4e 100644\n--- a/hw/riscv/spike.c\n+++ b/hw/riscv/spike.c\n@@ -281,9 +281,12 @@ static void spike_board_init(MachineState *machine)\n }\n }\n \n+ riscv_boot_info_init(&boot_info, &s->soc[0]);\n+\n /* Load firmware */\n if (firmware_name) {\n- firmware_end_addr = riscv_load_firmware(firmware_name,\n+ firmware_end_addr = riscv_load_firmware(machine, &boot_info,\n+ firmware_name,\n &firmware_load_addr,\n htif_symbol_callback);\n g_free(firmware_name);\n@@ -293,7 +296,6 @@ static void spike_board_init(MachineState *machine)\n create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base);\n \n /* Load kernel */\n- riscv_boot_info_init(&boot_info, &s->soc[0]);\n if (machine->kernel_filename) {\n kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,\n firmware_end_addr);\ndiff --git a/hw/riscv/virt.c b/hw/riscv/virt.c\nindex a1c323e66dfd..4501d5581b62 100644\n--- a/hw/riscv/virt.c\n+++ b/hw/riscv/virt.c\n@@ -1457,7 +1457,10 @@ static void virt_machine_done(Notifier *notifier, void *data)\n }\n }\n \n- firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,\n+ riscv_boot_info_init(&boot_info, &s->soc[0]);\n+\n+ firmware_end_addr = riscv_find_and_load_firmware(machine, &boot_info,\n+ firmware_name,\n &start_addr, NULL);\n \n pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]);\n@@ -1480,8 +1483,6 @@ static void virt_machine_done(Notifier *notifier, void *data)\n }\n }\n \n- riscv_boot_info_init(&boot_info, &s->soc[0]);\n-\n if (machine->kernel_filename && !kernel_entry) {\n kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,\n firmware_end_addr);\ndiff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c\nindex 436e51c1c593..247a0b5d1f21 100644\n--- a/hw/riscv/xiangshan_kmh.c\n+++ b/hw/riscv/xiangshan_kmh.c\n@@ -166,6 +166,7 @@ static void xiangshan_kmh_machine_init(MachineState *machine)\n const MemMapEntry *memmap = xiangshan_kmh_memmap;\n MemoryRegion *system_memory = get_system_memory();\n hwaddr start_addr = memmap[XIANGSHAN_KMH_DRAM].base;\n+ RISCVBootInfo boot_info;\n \n /* Initialize SoC */\n object_initialize_child(OBJECT(machine), \"soc\", &s->soc,\n@@ -177,13 +178,16 @@ static void xiangshan_kmh_machine_init(MachineState *machine)\n memmap[XIANGSHAN_KMH_DRAM].base,\n machine->ram);\n \n+ riscv_boot_info_init(&boot_info, &s->soc.cpus);\n+\n /* ROM reset vector */\n riscv_setup_rom_reset_vec(machine, &s->soc.cpus,\n start_addr,\n memmap[XIANGSHAN_KMH_ROM].base,\n memmap[XIANGSHAN_KMH_ROM].size, 0, 0);\n if (machine->firmware) {\n- riscv_load_firmware(machine->firmware, &start_addr, NULL);\n+ riscv_load_firmware(machine, &boot_info, machine->firmware,\n+ &start_addr, NULL);\n }\n \n /* Note: dtb has been integrated into firmware(OpenSBI) when compiling */\n","prefixes":["v2","2/4"]}