{"id":2223257,"url":"http://patchwork.ozlabs.org/api/patches/2223257/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414213108.66786-3-philmd@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260414213108.66786-3-philmd@linaro.org>","list_archive_url":null,"date":"2026-04-14T21:31:08","name":"[RFC,v4,2/2] target/mips: Translate MSA vector store opcode (ST.df)","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"052ea727b2ed16d29cebfb290e87a479042b3bd8","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414213108.66786-3-philmd@linaro.org/mbox/","series":[{"id":499894,"url":"http://patchwork.ozlabs.org/api/series/499894/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499894","date":"2026-04-14T21:31:06","name":"target/mips: Translate MSA vector load/store opcodes","version":4,"mbox":"http://patchwork.ozlabs.org/series/499894/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223257/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223257/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=C0fCKSmx;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::32b;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Replace helpers by translation.\n\nRemove legacy cpu_st*_data_ra() calls, replacing by\ntcg_gen_qemu_st() which allow to respect atomicity.\n\nRemove the ensure_writable_pages() hack and the bswap\nNxM helpers.\n\nSigned-off-by: Philippe Mathieu-Daudé \n---\n target/mips/tcg/msa_helper.h.inc | 8 ---\n target/mips/tcg/msa_helper.c | 104 -------------------------------\n target/mips/tcg/msa_translate.c | 54 ++++++++++++----\n 3 files changed, 42 insertions(+), 124 deletions(-)","diff":"diff --git a/target/mips/tcg/msa_helper.h.inc b/target/mips/tcg/msa_helper.h.inc\nindex 7ede16f327a..e994353056f 100644\n--- a/target/mips/tcg/msa_helper.h.inc\n+++ b/target/mips/tcg/msa_helper.h.inc\n@@ -432,11 +432,3 @@ DEF_HELPER_4(msa_ftint_s_df, void, env, i32, i32, i32)\n DEF_HELPER_4(msa_ftint_u_df, void, env, i32, i32, i32)\n DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32)\n DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32)\n-\n-#define MSALDST_PROTO(type) \\\n-DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl)\n-MSALDST_PROTO(b)\n-MSALDST_PROTO(h)\n-MSALDST_PROTO(w)\n-MSALDST_PROTO(d)\n-#undef MSALDST_PROTO\ndiff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c\nindex 3a0ba420b9d..28148ea9c8b 100644\n--- a/target/mips/tcg/msa_helper.c\n+++ b/target/mips/tcg/msa_helper.c\n@@ -8205,107 +8205,3 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,\n \n msa_move_v(pwd, pwx);\n }\n-\n-/* Data format min and max values */\n-#define DF_BITS(df) (1 << ((df) + 3))\n-\n-/* Element-by-element access macros */\n-#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))\n-\n-static inline uint64_t bswap16x4(uint64_t x)\n-{\n- uint64_t m = 0x00ff00ff00ff00ffull;\n- return ((x & m) << 8) | ((x >> 8) & m);\n-}\n-\n-static inline uint64_t bswap32x2(uint64_t x)\n-{\n- return ror64(bswap64(x), 32);\n-}\n-\n-#define MSA_PAGESPAN(x) \\\n- ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >= TARGET_PAGE_SIZE)\n-\n-static inline void ensure_writable_pages(CPUMIPSState *env,\n- target_ulong addr,\n- int mmu_idx,\n- uintptr_t retaddr)\n-{\n- /* FIXME: Probe the actual accesses (pass and use a size) */\n- if (unlikely(MSA_PAGESPAN(addr))) {\n- /* first page */\n- probe_write(env, addr, 0, mmu_idx, retaddr);\n- /* second page */\n- addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;\n- probe_write(env, addr, 0, mmu_idx, retaddr);\n- }\n-}\n-\n-void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,\n- target_ulong addr)\n-{\n- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n- int mmu_idx = mips_env_mmu_index(env);\n- uintptr_t ra = GETPC();\n-\n- ensure_writable_pages(env, addr, mmu_idx, ra);\n-\n- /* Store 8 bytes at a time. Vector element ordering makes this LE. */\n- cpu_stq_le_data_ra(env, addr + 0, pwd->d[0], ra);\n- cpu_stq_le_data_ra(env, addr + 8, pwd->d[1], ra);\n-}\n-\n-void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,\n- target_ulong addr)\n-{\n- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n- int mmu_idx = mips_env_mmu_index(env);\n- uintptr_t ra = GETPC();\n- uint64_t d0, d1;\n-\n- ensure_writable_pages(env, addr, mmu_idx, ra);\n-\n- /* Store 8 bytes at a time. See helper_msa_ld_h. */\n- d0 = pwd->d[0];\n- d1 = pwd->d[1];\n- if (mips_env_is_bigendian(env)) {\n- d0 = bswap16x4(d0);\n- d1 = bswap16x4(d1);\n- }\n- cpu_stq_le_data_ra(env, addr + 0, d0, ra);\n- cpu_stq_le_data_ra(env, addr + 8, d1, ra);\n-}\n-\n-void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,\n- target_ulong addr)\n-{\n- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n- int mmu_idx = mips_env_mmu_index(env);\n- uintptr_t ra = GETPC();\n- uint64_t d0, d1;\n-\n- ensure_writable_pages(env, addr, mmu_idx, ra);\n-\n- /* Store 8 bytes at a time. See helper_msa_ld_w. */\n- d0 = pwd->d[0];\n- d1 = pwd->d[1];\n- if (mips_env_is_bigendian(env)) {\n- d0 = bswap32x2(d0);\n- d1 = bswap32x2(d1);\n- }\n- cpu_stq_le_data_ra(env, addr + 0, d0, ra);\n- cpu_stq_le_data_ra(env, addr + 8, d1, ra);\n-}\n-\n-void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,\n- target_ulong addr)\n-{\n- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n- int mmu_idx = mips_env_mmu_index(env);\n- uintptr_t ra = GETPC();\n-\n- ensure_writable_pages(env, addr, mmu_idx, GETPC());\n-\n- cpu_stq_data_ra(env, addr + 0, pwd->d[0], ra);\n- cpu_stq_data_ra(env, addr + 8, pwd->d[1], ra);\n-}\ndiff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c\nindex 0ad8c2c0dc9..c48e5108fe9 100644\n--- a/target/mips/tcg/msa_translate.c\n+++ b/target/mips/tcg/msa_translate.c\n@@ -164,7 +164,6 @@ static inline bool check_msa_enabled(DisasContext *ctx)\n return true;\n }\n \n-typedef void gen_helper_piv(TCGv_ptr, TCGv_i32, TCGv);\n typedef void gen_helper_pii(TCGv_ptr, TCGv_i32, TCGv_i32);\n typedef void gen_helper_piii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);\n typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);\n@@ -175,9 +174,6 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);\n }; \\\n TRANS(NAME, trans_func, NAME##_tab[a->df])\n \n-#define TRANS_DF_iv(NAME, trans_func, gen_func) \\\n- TRANS_DF_x(iv, NAME, trans_func, gen_func)\n-\n #define TRANS_DF_ii(NAME, trans_func, gen_func) \\\n TRANS_DF_x(ii, NAME, trans_func, gen_func)\n \n@@ -801,25 +797,59 @@ static bool trans_LD(DisasContext *ctx, arg_msa_i *a)\n return true;\n }\n \n-static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a,\n- gen_helper_piv *gen_msa_ldst)\n+static bool trans_ST(DisasContext *ctx, arg_msa_i *a)\n {\n- TCGv taddr;\n+ TCGv_va addr;\n+ TCGv_i128 d16;\n+ MemOp mop;\n+ int d0 = a->wd << 1;\n+ int d1 = d0 + 1;\n \n if (!check_msa_enabled(ctx)) {\n return true;\n }\n \n- taddr = tcg_temp_new();\n+ addr = tcgv_va_temp_new();\n+ gen_base_offset_addr(ctx, addr, a->ws, a->sa << a->df);\n \n- gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df);\n- gen_msa_ldst(tcg_env, tcg_constant_i32(a->wd), taddr);\n+ mop = MO_128 | MO_LE;\n+ if (a->df == 0) {\n+ mop |= MO_ATOM_NONE;\n+ } else if (a->df == 3) {\n+ mop |= MO_ATOM_IFALIGN_PAIR;\n+ } else {\n+ mop |= MO_ATOM_SUBALIGN; /* slightly stronger than required */\n+ }\n+ mop |= a->df << MO_ASHIFT; /* MO_ALIGN */\n+\n+ d16 = tcg_temp_new_i128();\n+\n+ if (mo_endian(ctx) != MO_LE) {\n+ TCGv_i64 t0 = tcg_temp_new_i64();\n+ TCGv_i64 t1 = tcg_temp_new_i64();\n+\n+ if (a->df == 1) {\n+ tcg_gen_hswap_i64(t0, msa_wr_d[d0]);\n+ tcg_gen_hswap_i64(t1, msa_wr_d[d1]);\n+ tcg_gen_concat_i64_i128(d16, t0, t1);\n+ } else if (a->df == 2) {\n+ tcg_gen_wswap_i64(t0, msa_wr_d[d0]);\n+ tcg_gen_wswap_i64(t1, msa_wr_d[d1]);\n+ tcg_gen_concat_i64_i128(d16, t0, t1);\n+ } else {\n+ tcg_gen_ld_i128(d16, tcg_env,\n+ offsetof(CPUMIPSState, active_fpu.fpr[d0]));\n+ }\n+ } else {\n+ tcg_gen_ld_i128(d16, tcg_env,\n+ offsetof(CPUMIPSState, active_fpu.fpr[d0]));\n+ }\n+\n+ tcg_gen_qemu_st_i128(d16, addr, ctx->mem_idx, mop);\n \n return true;\n }\n \n-TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st);\n-\n static bool trans_LSA(DisasContext *ctx, arg_r *a)\n {\n return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa + 1);\n","prefixes":["RFC","v4","2/2"]}