{"id":2223256,"url":"http://patchwork.ozlabs.org/api/patches/2223256/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414213108.66786-2-philmd@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260414213108.66786-2-philmd@linaro.org>","list_archive_url":null,"date":"2026-04-14T21:31:07","name":"[RFC,v4,1/2] target/mips: Translate MSA vector load opcode (LD.df)","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"87adc956fe6e322ee228de2499899bddd7b1b93a","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414213108.66786-2-philmd@linaro.org/mbox/","series":[{"id":499894,"url":"http://patchwork.ozlabs.org/api/series/499894/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499894","date":"2026-04-14T21:31:06","name":"target/mips: Translate MSA vector load/store opcodes","version":4,"mbox":"http://patchwork.ozlabs.org/series/499894/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223256/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223256/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=EVmb7Byr;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::429;\n envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Replace helpers by translation.\n\nRemove legacy cpu_ld*_data_ra() calls, replacing by\ntcg_gen_qemu_ld() which allow to respect atomicity.\n\nSigned-off-by: Philippe Mathieu-Daudé \n---\n target/mips/tcg/msa_helper.h.inc | 1 -\n target/mips/tcg/msa_helper.c | 69 --------------------------------\n target/mips/tcg/msa_translate.c | 44 +++++++++++++++++++-\n 3 files changed, 43 insertions(+), 71 deletions(-)","diff":"diff --git a/target/mips/tcg/msa_helper.h.inc b/target/mips/tcg/msa_helper.h.inc\nindex 4963d1553a0..7ede16f327a 100644\n--- a/target/mips/tcg/msa_helper.h.inc\n+++ b/target/mips/tcg/msa_helper.h.inc\n@@ -434,7 +434,6 @@ DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32)\n DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32)\n \n #define MSALDST_PROTO(type) \\\n-DEF_HELPER_3(msa_ld_ ## type, void, env, i32, tl) \\\n DEF_HELPER_3(msa_st_ ## type, void, env, i32, tl)\n MSALDST_PROTO(b)\n MSALDST_PROTO(h)\ndiff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c\nindex f554b3d10ee..3a0ba420b9d 100644\n--- a/target/mips/tcg/msa_helper.c\n+++ b/target/mips/tcg/msa_helper.c\n@@ -8223,75 +8223,6 @@ static inline uint64_t bswap32x2(uint64_t x)\n return ror64(bswap64(x), 32);\n }\n \n-void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd,\n- target_ulong addr)\n-{\n- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n- uintptr_t ra = GETPC();\n- uint64_t d0, d1;\n-\n- /* Load 8 bytes at a time. Vector element ordering makes this LE. */\n- d0 = cpu_ldq_le_data_ra(env, addr + 0, ra);\n- d1 = cpu_ldq_le_data_ra(env, addr + 8, ra);\n- pwd->d[0] = d0;\n- pwd->d[1] = d1;\n-}\n-\n-void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd,\n- target_ulong addr)\n-{\n- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n- uintptr_t ra = GETPC();\n- uint64_t d0, d1;\n-\n- /*\n- * Load 8 bytes at a time. Use little-endian load, then for\n- * big-endian target, we must then swap the four halfwords.\n- */\n- d0 = cpu_ldq_le_data_ra(env, addr + 0, ra);\n- d1 = cpu_ldq_le_data_ra(env, addr + 8, ra);\n- if (mips_env_is_bigendian(env)) {\n- d0 = bswap16x4(d0);\n- d1 = bswap16x4(d1);\n- }\n- pwd->d[0] = d0;\n- pwd->d[1] = d1;\n-}\n-\n-void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd,\n- target_ulong addr)\n-{\n- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n- uintptr_t ra = GETPC();\n- uint64_t d0, d1;\n-\n- /*\n- * Load 8 bytes at a time. Use little-endian load, then for\n- * big-endian target, we must then bswap the two words.\n- */\n- d0 = cpu_ldq_le_data_ra(env, addr + 0, ra);\n- d1 = cpu_ldq_le_data_ra(env, addr + 8, ra);\n- if (mips_env_is_bigendian(env)) {\n- d0 = bswap32x2(d0);\n- d1 = bswap32x2(d1);\n- }\n- pwd->d[0] = d0;\n- pwd->d[1] = d1;\n-}\n-\n-void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,\n- target_ulong addr)\n-{\n- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);\n- uintptr_t ra = GETPC();\n- uint64_t d0, d1;\n-\n- d0 = cpu_ldq_data_ra(env, addr + 0, ra);\n- d1 = cpu_ldq_data_ra(env, addr + 8, ra);\n- pwd->d[0] = d0;\n- pwd->d[1] = d1;\n-}\n-\n #define MSA_PAGESPAN(x) \\\n ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >= TARGET_PAGE_SIZE)\n \ndiff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c\nindex 82b149922fa..0ad8c2c0dc9 100644\n--- a/target/mips/tcg/msa_translate.c\n+++ b/target/mips/tcg/msa_translate.c\n@@ -758,6 +758,49 @@ TRANS(FTINT_U, trans_msa_2rf, gen_helper_msa_ftint_u_df);\n TRANS(FFINT_S, trans_msa_2rf, gen_helper_msa_ffint_s_df);\n TRANS(FFINT_U, trans_msa_2rf, gen_helper_msa_ffint_u_df);\n \n+static bool trans_LD(DisasContext *ctx, arg_msa_i *a)\n+{\n+ TCGv_va addr;\n+ TCGv_i128 d16;\n+ MemOp mop;\n+ int d0 = a->wd << 1;\n+ int d1 = d0 + 1;\n+\n+ if (!check_msa_enabled(ctx)) {\n+ return true;\n+ }\n+\n+ addr = tcgv_va_temp_new();\n+ gen_base_offset_addr(ctx, addr, a->ws, a->sa << a->df);\n+\n+ mop = MO_128 | MO_LE;\n+ if (a->df == 0) {\n+ mop |= MO_ATOM_NONE;\n+ } else if (a->df == 3) {\n+ mop |= MO_ATOM_IFALIGN_PAIR;\n+ } else {\n+ mop |= MO_ATOM_SUBALIGN; /* slightly stronger than required */\n+ }\n+ mop |= a->df << MO_ASHIFT; /* MO_ALIGN */\n+\n+ d16 = tcg_temp_new_i128();\n+ tcg_gen_qemu_ld_i128(d16, addr, ctx->mem_idx, mop);\n+\n+ tcg_gen_st_i128(d16, tcg_env, offsetof(CPUMIPSState, active_fpu.fpr[d0]));\n+\n+ if (mo_endian(ctx) != MO_LE) {\n+ if (a->df == 1) {\n+ tcg_gen_hswap_i64(msa_wr_d[d0], msa_wr_d[d0]);\n+ tcg_gen_hswap_i64(msa_wr_d[d1], msa_wr_d[d1]);\n+ } else if (a->df == 2) {\n+ tcg_gen_wswap_i64(msa_wr_d[d0], msa_wr_d[d0]);\n+ tcg_gen_wswap_i64(msa_wr_d[d1], msa_wr_d[d1]);\n+ }\n+ }\n+\n+ return true;\n+}\n+\n static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a,\n gen_helper_piv *gen_msa_ldst)\n {\n@@ -775,7 +818,6 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a,\n return true;\n }\n \n-TRANS_DF_iv(LD, trans_msa_ldst, gen_helper_msa_ld);\n TRANS_DF_iv(ST, trans_msa_ldst, gen_helper_msa_st);\n \n static bool trans_LSA(DisasContext *ctx, arg_r *a)\n","prefixes":["RFC","v4","1/2"]}