{"id":2223238,"url":"http://patchwork.ozlabs.org/api/patches/2223238/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414182313.1691519-12-gaurav.sharma_7@nxp.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260414182313.1691519-12-gaurav.sharma_7@nxp.com>","list_archive_url":null,"date":"2026-04-14T18:23:09","name":"[PATCHv6,11/15] hw/arm/fsl-imx8mm: Adding support for Watchdog Timers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e07544b4836524427b90a2ad71827189dba8e589","submitter":{"id":92057,"url":"http://patchwork.ozlabs.org/api/people/92057/?format=json","name":"Gaurav Sharma","email":"gaurav.sharma_7@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414182313.1691519-12-gaurav.sharma_7@nxp.com/mbox/","series":[{"id":499884,"url":"http://patchwork.ozlabs.org/api/series/499884/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499884","date":"2026-04-14T18:23:11","name":"Adding comprehensive support for i.MX8MM EVK board","version":1,"mbox":"http://patchwork.ozlabs.org/series/499884/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223238/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223238/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":"legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Tue, 14 Apr 2026 14:23:25 -0400","from inva021.nxp.com (localhost [127.0.0.1])\n by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id A46E92028D2;\n Tue, 14 Apr 2026 20:23:21 +0200 (CEST)","from aprdc01srsp001v.ap-rdc01.nxp.com\n (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16])\n by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 6FBEF201EC1;\n Tue, 14 Apr 2026 20:23:21 +0200 (CEST)","from lsv031015.swis.in-blr01.nxp.com\n (lsv031015.swis.in-blr01.nxp.com [10.12.177.77])\n by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id E0367180222A;\n Wed, 15 Apr 2026 02:23:20 +0800 (+08)"],"From":"Gaurav Sharma ","To":"qemu-devel@nongnu.org","Cc":"pbonzini@redhat.com, peter.maydell@linaro.org,\n Gaurav Sharma ,\n Philippe Mathieu-Daude ","Subject":"[PATCHv6 11/15] hw/arm/fsl-imx8mm: Adding support for Watchdog Timers","Date":"Tue, 14 Apr 2026 23:53:09 +0530","Message-Id":"<20260414182313.1691519-12-gaurav.sharma_7@nxp.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260414182313.1691519-1-gaurav.sharma_7@nxp.com>","References":"<20260414182313.1691519-1-gaurav.sharma_7@nxp.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Virus-Scanned":"ClamAV using ClamSMTP","Received-SPF":"pass client-ip=92.121.34.21;\n envelope-from=gaurav.sharma_7@nxp.com; helo=inva021.nxp.com","X-Spam_score_int":"-41","X-Spam_score":"-4.2","X-Spam_bar":"----","X-Spam_report":"(-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"It enables emulation of WDT in iMX8MM\nAdded WDT IRQ lines\n\nReviewed-by: Philippe Mathieu-Daude \nReviewed-by: Peter Maydell \nSigned-off-by: Gaurav Sharma \n---\n hw/arm/Kconfig | 1 +\n hw/arm/fsl-imx8mm.c | 28 ++++++++++++++++++++++++++++\n include/hw/arm/fsl-imx8mm.h | 7 +++++++\n 3 files changed, 36 insertions(+)","diff":"diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex 97ff6d9716..946c9eb693 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -630,6 +630,7 @@ config FSL_IMX8MM\n select SDHCI\n select PCI_EXPRESS_DESIGNWARE\n select PCI_EXPRESS_FSL_IMX8M_PHY\n+ select WDT_IMX2\n \n config FSL_IMX8MM_EVK\n bool\ndiff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex f433beeaf2..34645555d6 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -200,6 +200,11 @@ static void fsl_imx8mm_init(Object *obj)\n object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);\n }\n \n+ for (i = 0; i < FSL_IMX8MM_NUM_WDTS; i++) {\n+ g_autofree char *name = g_strdup_printf(\"wdt%d\", i);\n+ object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT);\n+ }\n+\n object_initialize_child(obj, \"pcie\", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);\n object_initialize_child(obj, \"pcie_phy\", &s->pcie_phy,\n TYPE_FSL_IMX8M_PCIE_PHY);\n@@ -496,6 +501,28 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0,\n fsl_imx8mm_memmap[FSL_IMX8MM_SNVS_HP].addr);\n \n+ /* Watchdogs */\n+ for (i = 0; i < FSL_IMX8MM_NUM_WDTS; i++) {\n+ static const struct {\n+ hwaddr addr;\n+ unsigned int irq;\n+ } wdog_table[FSL_IMX8MM_NUM_WDTS] = {\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_WDOG1].addr, FSL_IMX8MM_WDOG1_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_WDOG2].addr, FSL_IMX8MM_WDOG2_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_WDOG3].addr, FSL_IMX8MM_WDOG3_IRQ },\n+ };\n+\n+ object_property_set_bool(OBJECT(&s->wdt[i]), \"pretimeout-support\",\n+ true, &error_abort);\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {\n+ return;\n+ }\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, wdog_table[i].addr);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,\n+ qdev_get_gpio_in(gicdev, wdog_table[i].irq));\n+ }\n+\n /* PCIe */\n if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) {\n return;\n@@ -537,6 +564,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n case FSL_IMX8MM_SNVS_HP:\n case FSL_IMX8MM_UART1 ... FSL_IMX8MM_UART4:\n case FSL_IMX8MM_USDHC1 ... FSL_IMX8MM_USDHC3:\n+ case FSL_IMX8MM_WDOG1 ... FSL_IMX8MM_WDOG3:\n /* device implemented and treated above */\n break;\n \ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex 13c044412a..fd62b19a87 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -22,6 +22,7 @@\n #include \"hw/pci-host/fsl_imx8m_phy.h\"\n #include \"hw/sd/sdhci.h\"\n #include \"hw/ssi/imx_spi.h\"\n+#include \"hw/watchdog/wdt_imx2.h\"\n #include \"qom/object.h\"\n #include \"qemu/units.h\"\n \n@@ -39,6 +40,7 @@ enum FslImx8mmConfiguration {\n FSL_IMX8MM_NUM_IRQS = 128,\n FSL_IMX8MM_NUM_UARTS = 4,\n FSL_IMX8MM_NUM_USDHCS = 3,\n+ FSL_IMX8MM_NUM_WDTS = 3,\n };\n \n struct FslImx8mmState {\n@@ -55,6 +57,7 @@ struct FslImx8mmState {\n IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];\n MemoryRegion ocram;\n SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS];\n+ IMX2WdtState wdt[FSL_IMX8MM_NUM_WDTS];\n DesignwarePCIEHost pcie;\n FslImx8mPciePhyState pcie_phy;\n };\n@@ -200,6 +203,10 @@ enum FslImx8mmIrqs {\n FSL_IMX8MM_GPIO5_LOW_IRQ = 72,\n FSL_IMX8MM_GPIO5_HIGH_IRQ = 73,\n \n+ FSL_IMX8MM_WDOG1_IRQ = 78,\n+ FSL_IMX8MM_WDOG2_IRQ = 79,\n+ FSL_IMX8MM_WDOG3_IRQ = 10,\n+\n FSL_IMX8MM_PCI_INTA_IRQ = 122,\n FSL_IMX8MM_PCI_INTB_IRQ = 123,\n FSL_IMX8MM_PCI_INTC_IRQ = 124,\n","prefixes":["PATCHv6","11/15"]}