{"id":2223176,"url":"http://patchwork.ozlabs.org/api/patches/2223176/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20260414161552.729405-1-rearnsha@arm.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260414161552.729405-1-rearnsha@arm.com>","list_archive_url":null,"date":"2026-04-14T16:15:52","name":"[committed] arm: apply stronger checks on conditional-compare patterns [PR123102]","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6a2d69c0c266bbd957b38cac2c49b0d17a66d622","submitter":{"id":4378,"url":"http://patchwork.ozlabs.org/api/people/4378/?format=json","name":"Richard Earnshaw","email":"rearnsha@arm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20260414161552.729405-1-rearnsha@arm.com/mbox/","series":[{"id":499865,"url":"http://patchwork.ozlabs.org/api/series/499865/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=499865","date":"2026-04-14T16:15:52","name":"[committed] arm: apply stronger checks on conditional-compare patterns [PR123102]","version":1,"mbox":"http://patchwork.ozlabs.org/series/499865/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223176/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223176/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=foss header.b=j8sc1Tb3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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a=rsa-sha256; d=sourceware.org; s=key;\n t=1776183367; c=relaxed/simple;\n bh=DW8DMBicYi/xvBEurZmNICigO9jtBpUB8E93rbKavXY=;\n h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version;\n b=AeUXQ4JZORMXjaWkcqKG0dZzrOC9lio8SAqvzLsKOBlmxEEMdaQ42I9nwvNUYtcqwgFmRI20XNOdfsyCKXX8mP0Rqa5Q5MWw5NxeIqQWHelspYn2AwtYj3RG43ttYAVLHFzoMYb16f5NbAJBvksvs0scUPYLNu/DsVHYhDH5a/I=","ARC-Authentication-Results":"i=1; server2.sourceware.org","DKIM-Signature":"v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss;\n t=1776183366; bh=DW8DMBicYi/xvBEurZmNICigO9jtBpUB8E93rbKavXY=;\n h=From:To:Cc:Subject:Date:From;\n b=j8sc1Tb3hKQSd8TL9uwp3rJoH48nDojpaQ7kKkI/l3XdZPcxMQfLUtAhbaPu5AGKx\n DienJeSNAI6+HEnf4jhajlfZ+DvZXO79+uQIhwAPi6S2mkTHoLC5/gWnebbDMncvdh\n YtoSBzIL0Z0tfsOxDOA43pcUp0y3irX8UW2XAcvM=","From":"Richard Earnshaw ","To":"gcc-patches@gcc.gnu.org","Cc":"Richard Earnshaw ","Subject":"[committed] arm: apply stronger checks on conditional-compare\n patterns [PR123102]","Date":"Tue, 14 Apr 2026 17:15:52 +0100","Message-ID":"<20260414161552.729405-1-rearnsha@arm.com>","X-Mailer":"git-send-email 2.43.0","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"If a conditional compare operation is generated during expand, then\ncombine may try to substitute into it in order to generate better code;\nbut if it does so, we need to validate that the optimized sequence is\nstill a valid conditional compare. We were skipping those checks and\nthat can lead to wrong code being generated.\n\ngcc/ChangeLog:\n\tPR target/123102\n\t* config/arm/arm.md (*cmp_ite0): Apply stricter checks on the\n\tcomparison mode.\n\t(*cmp_ite1, *cmp_and, *cmp_ior): Likewise.\n---\n\nNote, I haven't added a new test for this. The testcase in the PR is\npretty fragile as it depends on a constant not being propagated during\ntree optimization, but then picked up during RTL optimization; there\ndoesn't seem to be a reliable way of ensuring that such a test will\nremain useful into the future as the compiler becomes yet more\ncapable.\n\n gcc/config/arm/arm.md | 26 ++++++++++++++++++++++----\n 1 file changed, 22 insertions(+), 4 deletions(-)","diff":"diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md\nindex d9ce482838b..2a72dde3647 100644\n--- a/gcc/config/arm/arm.md\n+++ b/gcc/config/arm/arm.md\n@@ -10133,6 +10133,7 @@ (define_insn \"*cond_sub\"\n (set_attr \"type\" \"multiple\")]\n )\n \n+;; (pred4 && pred5) != 0\n (define_insn \"*cmp_ite0\"\n [(set (match_operand 6 \"dominant_cc_register\" \"\")\n \t(compare\n@@ -10149,7 +10150,11 @@ (define_insn \"*cmp_ite0\"\n \t \"lPy,rI,L,lPy,lPy,rI,rI,L,L\")])\n \t (const_int 0))\n \t (const_int 0)))]\n- \"TARGET_32BIT\"\n+ \"TARGET_32BIT\n+ && GET_MODE (operands[6]) != CCmode\n+ && (GET_MODE (operands[6])\n+ == arm_select_dominance_cc_mode (operands[4], operands[5],\n+\t\t\t\t\tDOM_CC_X_AND_Y))\"\n \"*\n {\n static const char * const cmp1[NUM_OF_COND_CMP][2] =\n@@ -10216,6 +10221,7 @@ (define_insn \"*cmp_ite0\"\n (const_int 10))])]\n )\n \n+;; (!pred4 || pred5) != 0\n (define_insn \"*cmp_ite1\"\n [(set (match_operand 6 \"dominant_cc_register\" \"\")\n \t(compare\n@@ -10232,7 +10238,11 @@ (define_insn \"*cmp_ite1\"\n \t \"lPy,rI,L,lPy,lPy,rI,rI,L,L\")])\n \t (const_int 1))\n \t (const_int 0)))]\n- \"TARGET_32BIT\"\n+ \"TARGET_32BIT\n+ && GET_MODE (operands[6]) != CCmode\n+ && (GET_MODE (operands[6])\n+ == arm_select_dominance_cc_mode (operands[4], operands[5],\n+\t\t\t\t\tDOM_CC_NX_OR_Y))\"\n \"*\n {\n static const char * const cmp1[NUM_OF_COND_CMP][2] =\n@@ -10315,7 +10325,11 @@ (define_insn \"*cmp_and\"\n \t (match_operand:SI 3 \"arm_add_operand\"\n \t \"lPy,rI,L,lPy,lPy,r,rI,rI,L,L\")]))\n \t (const_int 0)))]\n- \"TARGET_32BIT\"\n+ \"TARGET_32BIT\n+ && GET_MODE (operands[6]) != CCmode\n+ && (GET_MODE (operands[6])\n+ == arm_select_dominance_cc_mode (operands[4], operands[5],\n+\t\t\t\t\tDOM_CC_X_AND_Y))\"\n \"*\n {\n static const char *const cmp1[NUM_OF_COND_CMP][2] =\n@@ -10400,7 +10414,11 @@ (define_insn \"*cmp_ior\"\n \t (match_operand:SI 3 \"arm_add_operand\"\n \t \"lPy,rI,L,lPy,lPy,r,rI,rI,L,L\")]))\n \t (const_int 0)))]\n- \"TARGET_32BIT\"\n+ \"TARGET_32BIT\n+ && GET_MODE (operands[6]) != CCmode\n+ && (GET_MODE (operands[6])\n+ == arm_select_dominance_cc_mode (operands[4], operands[5],\n+\t\t\t\t\tDOM_CC_X_OR_Y))\"\n \"*\n {\n static const char *const cmp1[NUM_OF_COND_CMP][2] =\n","prefixes":["committed"]}