{"id":2223163,"url":"http://patchwork.ozlabs.org/api/patches/2223163/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414155433.483186-2-magnuskulke@linux.microsoft.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260414155433.483186-2-magnuskulke@linux.microsoft.com>","list_archive_url":null,"date":"2026-04-14T15:54:25","name":"[v4,1/9] accel/mshv: use mshv_create_partition_v2 payload","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"fd68535cfdcdbc5c7e44e8c333e1a96a44f1f744","submitter":{"id":90753,"url":"http://patchwork.ozlabs.org/api/people/90753/?format=json","name":"Magnus Kulke","email":"magnuskulke@linux.microsoft.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414155433.483186-2-magnuskulke@linux.microsoft.com/mbox/","series":[{"id":499862,"url":"http://patchwork.ozlabs.org/api/series/499862/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499862","date":"2026-04-14T15:54:24","name":"Support QEMU cpu models in MSHV accelerator","version":4,"mbox":"http://patchwork.ozlabs.org/series/499862/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223163/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223163/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=HpLteX27;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1776182081;\n bh=UbQCp/z8d0UWo4lIFYXYd0mdek+SJnwAX0PfzqX1kKY=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=HpLteX27zbvXz+TKIqQ8V9RyIBtlOJJoddWHi3+KTJ1aifvrvdVBwh3pYwLpAaHWL\n poiHnAZditJLybCofppgU9YrJqTaVZiNUUdmcF3SRnfIttSWqR1gpl7doF33f9W0tg\n ulIGIRGYW34G9eovH/S6tysUNmunrTQ46nHGo2YY=","From":"Magnus Kulke ","To":"qemu-devel@nongnu.org","Cc":"Wei Liu , Wei Liu ,\n Magnus Kulke ,\n Magnus Kulke , Zhao Liu ,\n Paolo Bonzini ","Subject":"[PATCH v4 1/9] accel/mshv: use mshv_create_partition_v2 payload","Date":"Tue, 14 Apr 2026 17:54:25 +0200","Message-Id":"<20260414155433.483186-2-magnuskulke@linux.microsoft.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260414155433.483186-1-magnuskulke@linux.microsoft.com>","References":"<20260414155433.483186-1-magnuskulke@linux.microsoft.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=13.77.154.182;\n envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com","X-Spam_score_int":"-42","X-Spam_score":"-4.3","X-Spam_bar":"----","X-Spam_report":"(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"When using the extended request format we can instruct the hypervisor to\nprovision enough space for requested XSAVE features. This is required\nfor supporting QEMU models provided via the -cpu flag properly.\n\nSigned-off-by: Magnus Kulke \nAcked-by: Wei Liu \nReviewed-by: Anirudh Rayabharam (Microsoft) \n---\n accel/mshv/mshv-all.c | 71 ++++++++++--\n include/hw/hyperv/hvgdk_mini.h | 2 +\n include/hw/hyperv/hvhdk.h | 195 +++++++++++++++++++++++++++++++++\n 3 files changed, 261 insertions(+), 7 deletions(-)","diff":"diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c\nindex d4cc7f5371..c50641f174 100644\n--- a/accel/mshv/mshv-all.c\n+++ b/accel/mshv/mshv-all.c\n@@ -110,21 +110,78 @@ static int resume_vm(int vm_fd)\n return 0;\n }\n \n+static int get_host_partition_property(int mshv_fd, uint32_t property_code,\n+ uint64_t *value)\n+{\n+ int ret;\n+ struct hv_input_get_partition_property in = {0};\n+ struct hv_output_get_partition_property out = {0};\n+ struct mshv_root_hvcall args = {0};\n+\n+ in.property_code = property_code;\n+\n+ args.code = HVCALL_GET_PARTITION_PROPERTY;\n+ args.in_sz = sizeof(in);\n+ args.in_ptr = (uint64_t)∈\n+ args.out_sz = sizeof(out);\n+ args.out_ptr = (uint64_t)&out;\n+\n+ ret = ioctl(mshv_fd, MSHV_ROOT_HVCALL, &args);\n+ if (ret < 0) {\n+ error_report(\"Failed to get host partition property bank: %s\",\n+ strerror(errno));\n+ return -1;\n+ }\n+\n+ *value = out.property_value;\n+ return 0;\n+}\n+\n static int create_partition(int mshv_fd, int *vm_fd)\n {\n int ret;\n- struct mshv_create_partition args = {0};\n+ uint64_t pt_flags, host_proc_features;\n+ union hv_partition_processor_xsave_features disabled_xsave_features;\n+ struct mshv_create_partition_v2 args = {0};\n+\n+ QEMU_BUILD_BUG_ON(MSHV_NUM_CPU_FEATURES_BANKS != 2);\n \n /* Initialize pt_flags with the desired features */\n- uint64_t pt_flags = (1ULL << MSHV_PT_BIT_LAPIC) |\n- (1ULL << MSHV_PT_BIT_X2APIC) |\n- (1ULL << MSHV_PT_BIT_GPA_SUPER_PAGES);\n+ pt_flags = (1ULL << MSHV_PT_BIT_LAPIC) |\n+ (1ULL << MSHV_PT_BIT_X2APIC) |\n+ (1ULL << MSHV_PT_BIT_GPA_SUPER_PAGES) |\n+ (1ULL << MSHV_PT_BIT_CPU_AND_XSAVE_FEATURES);\n+\n+ /* enable all */\n+ disabled_xsave_features.as_uint64 = 0;\n+\n+ /*\n+ * query host for supported processor features and disable unsupported\n+ * features: (0 means supported, 1 means disabled, hence the negation)\n+ */\n+ ret = get_host_partition_property(mshv_fd,\n+ HV_PARTITION_PROPERTY_PROCESSOR_FEATURES0,\n+ &host_proc_features);\n+ if (ret < 0) {\n+ error_report(\"Failed to get host processor feature bank 0\");\n+ return -1;\n+ }\n+ args.pt_cpu_fbanks[0] = ~host_proc_features;\n \n- /* Set default isolation type */\n- uint64_t pt_isolation = MSHV_PT_ISOLATION_NONE;\n+ ret = get_host_partition_property(mshv_fd,\n+ HV_PARTITION_PROPERTY_PROCESSOR_FEATURES1,\n+ &host_proc_features);\n+ if (ret < 0) {\n+ error_report(\"Failed to get host processor feature bank 1\");\n+ return -1;\n+ }\n+ args.pt_cpu_fbanks[1] = ~host_proc_features;\n \n+ /* populate args structure */\n args.pt_flags = pt_flags;\n- args.pt_isolation = pt_isolation;\n+ args.pt_isolation = MSHV_PT_ISOLATION_NONE;\n+ args.pt_disabled_xsave = disabled_xsave_features.as_uint64;\n+ args.pt_num_cpu_fbanks = MSHV_NUM_CPU_FEATURES_BANKS;\n \n ret = ioctl(mshv_fd, MSHV_CREATE_PARTITION, &args);\n if (ret < 0) {\ndiff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h\nindex c3a8f33280..367519143e 100644\n--- a/include/hw/hyperv/hvgdk_mini.h\n+++ b/include/hw/hyperv/hvgdk_mini.h\n@@ -454,6 +454,8 @@ typedef struct hv_input_set_vp_registers {\n struct hv_register_assoc elements[];\n } QEMU_PACKED hv_input_set_vp_registers;\n \n+#define MSHV_VP_MAX_REGISTERS 128\n+\n union hv_interrupt_control {\n uint64_t as_uint64;\n struct {\ndiff --git a/include/hw/hyperv/hvhdk.h b/include/hw/hyperv/hvhdk.h\nindex 41af743847..9ad16c47da 100644\n--- a/include/hw/hyperv/hvhdk.h\n+++ b/include/hw/hyperv/hvhdk.h\n@@ -11,6 +11,16 @@\n \n #define HV_PARTITION_SYNTHETIC_PROCESSOR_FEATURES_BANKS 1\n \n+struct hv_input_get_partition_property {\n+ uint64_t partition_id;\n+ uint32_t property_code; /* enum hv_partition_property_code */\n+ uint32_t padding;\n+} QEMU_PACKED;\n+\n+struct hv_output_get_partition_property {\n+ uint64_t property_value;\n+} QEMU_PACKED;\n+\n struct hv_input_set_partition_property {\n uint64_t partition_id;\n uint32_t property_code; /* enum hv_partition_property_code */\n@@ -161,6 +171,191 @@ union hv_partition_synthetic_processor_features {\n };\n };\n \n+union hv_partition_processor_xsave_features {\n+ struct {\n+ uint64_t xsave_support:1;\n+ uint64_t xsaveopt_support:1;\n+ uint64_t avx_support:1;\n+ uint64_t avx2_support:1;\n+ uint64_t fma_support:1;\n+ uint64_t mpx_support:1;\n+ uint64_t avx512_support:1;\n+ uint64_t avx512_dq_support:1;\n+ uint64_t avx512_cd_support:1;\n+ uint64_t avx512_bw_support:1;\n+ uint64_t avx512_vl_support:1;\n+ uint64_t xsave_comp_support:1;\n+ uint64_t xsave_supervisor_support:1;\n+ uint64_t xcr1_support:1;\n+ uint64_t avx512_bitalg_support:1;\n+ uint64_t avx512_i_fma_support:1;\n+ uint64_t avx512_v_bmi_support:1;\n+ uint64_t avx512_v_bmi2_support:1;\n+ uint64_t avx512_vnni_support:1;\n+ uint64_t gfni_support:1;\n+ uint64_t vaes_support:1;\n+ uint64_t avx512_v_popcntdq_support:1;\n+ uint64_t vpclmulqdq_support:1;\n+ uint64_t avx512_bf16_support:1;\n+ uint64_t avx512_vp2_intersect_support:1;\n+ uint64_t avx512_fp16_support:1;\n+ uint64_t xfd_support:1;\n+ uint64_t amx_tile_support:1;\n+ uint64_t amx_bf16_support:1;\n+ uint64_t amx_int8_support:1;\n+ uint64_t avx_vnni_support:1;\n+ uint64_t avx_ifma_support:1;\n+ uint64_t avx_ne_convert_support:1;\n+ uint64_t avx_vnni_int8_support:1;\n+ uint64_t avx_vnni_int16_support:1;\n+ uint64_t avx10_1_256_support:1;\n+ uint64_t avx10_1_512_support:1;\n+ uint64_t amx_fp16_support:1;\n+ uint64_t reserved1:26;\n+ };\n+ uint64_t as_uint64;\n+};\n+\n+#define HV_PARTITION_PROCESSOR_FEATURES_BANKS 2\n+#define HV_PARTITION_PROCESSOR_FEATURES_RESERVEDBANK1_BITFIELD_COUNT 4\n+\n+\n+union hv_partition_processor_features {\n+ uint64_t as_uint64[HV_PARTITION_PROCESSOR_FEATURES_BANKS];\n+ struct {\n+ uint64_t sse3_support:1;\n+ uint64_t lahf_sahf_support:1;\n+ uint64_t ssse3_support:1;\n+ uint64_t sse4_1_support:1;\n+ uint64_t sse4_2_support:1;\n+ uint64_t sse4a_support:1;\n+ uint64_t xop_support:1;\n+ uint64_t pop_cnt_support:1;\n+ uint64_t cmpxchg16b_support:1;\n+ uint64_t altmovcr8_support:1;\n+ uint64_t lzcnt_support:1;\n+ uint64_t mis_align_sse_support:1;\n+ uint64_t mmx_ext_support:1;\n+ uint64_t amd3dnow_support:1;\n+ uint64_t extended_amd3dnow_support:1;\n+ uint64_t page_1gb_support:1;\n+ uint64_t aes_support:1;\n+ uint64_t pclmulqdq_support:1;\n+ uint64_t pcid_support:1;\n+ uint64_t fma4_support:1;\n+ uint64_t f16c_support:1;\n+ uint64_t rd_rand_support:1;\n+ uint64_t rd_wr_fs_gs_support:1;\n+ uint64_t smep_support:1;\n+ uint64_t enhanced_fast_string_support:1;\n+ uint64_t bmi1_support:1;\n+ uint64_t bmi2_support:1;\n+ uint64_t hle_support_deprecated:1;\n+ uint64_t rtm_support_deprecated:1;\n+ uint64_t movbe_support:1;\n+ uint64_t npiep1_support:1;\n+ uint64_t dep_x87_fpu_save_support:1;\n+ uint64_t rd_seed_support:1;\n+ uint64_t adx_support:1;\n+ uint64_t intel_prefetch_support:1;\n+ uint64_t smap_support:1;\n+ uint64_t hle_support:1;\n+ uint64_t rtm_support:1;\n+ uint64_t rdtscp_support:1;\n+ uint64_t clflushopt_support:1;\n+ uint64_t clwb_support:1;\n+ uint64_t sha_support:1;\n+ uint64_t x87_pointers_saved_support:1;\n+ uint64_t invpcid_support:1;\n+ uint64_t ibrs_support:1;\n+ uint64_t stibp_support:1;\n+ uint64_t ibpb_support:1;\n+ uint64_t unrestricted_guest_support:1;\n+ uint64_t mdd_support:1;\n+ uint64_t fast_short_rep_mov_support:1;\n+ uint64_t l1dcache_flush_support:1;\n+ uint64_t rdcl_no_support:1;\n+ uint64_t ibrs_all_support:1;\n+ uint64_t skip_l1df_support:1;\n+ uint64_t ssb_no_support:1;\n+ uint64_t rsb_a_no_support:1;\n+ uint64_t virt_spec_ctrl_support:1;\n+ uint64_t rd_pid_support:1;\n+ uint64_t umip_support:1;\n+ uint64_t mbs_no_support:1;\n+ uint64_t mb_clear_support:1;\n+ uint64_t taa_no_support:1;\n+ uint64_t tsx_ctrl_support:1;\n+ uint64_t reserved_bank0:1;\n+\n+ /* N.B. Begin bank 1 processor features. */\n+ uint64_t a_count_m_count_support:1;\n+ uint64_t tsc_invariant_support:1;\n+ uint64_t cl_zero_support:1;\n+ uint64_t rdpru_support:1;\n+ uint64_t la57_support:1;\n+ uint64_t mbec_support:1;\n+ uint64_t nested_virt_support:1;\n+ uint64_t psfd_support:1;\n+ uint64_t cet_ss_support:1;\n+ uint64_t cet_ibt_support:1;\n+ uint64_t vmx_exception_inject_support:1;\n+ uint64_t enqcmd_support:1;\n+ uint64_t umwait_tpause_support:1;\n+ uint64_t movdiri_support:1;\n+ uint64_t movdir64b_support:1;\n+ uint64_t cldemote_support:1;\n+ uint64_t serialize_support:1;\n+ uint64_t tsc_deadline_tmr_support:1;\n+ uint64_t tsc_adjust_support:1;\n+ uint64_t fzl_rep_movsb:1;\n+ uint64_t fs_rep_stosb:1;\n+ uint64_t fs_rep_cmpsb:1;\n+ uint64_t tsx_ld_trk_support:1;\n+ uint64_t vmx_ins_outs_exit_info_support:1;\n+ uint64_t hlat_support:1;\n+ uint64_t sbdr_ssdp_no_support:1;\n+ uint64_t fbsdp_no_support:1;\n+ uint64_t psdp_no_support:1;\n+ uint64_t fb_clear_support:1;\n+ uint64_t btc_no_support:1;\n+ uint64_t ibpb_rsb_flush_support:1;\n+ uint64_t stibp_always_on_support:1;\n+ uint64_t perf_global_ctrl_support:1;\n+ uint64_t npt_execute_only_support:1;\n+ uint64_t npt_ad_flags_support:1;\n+ uint64_t npt1_gb_page_support:1;\n+ uint64_t amd_processor_topology_node_id_support:1;\n+ uint64_t local_machine_check_support:1;\n+ uint64_t extended_topology_leaf_fp256_amd_support:1;\n+ uint64_t gds_no_support:1;\n+ uint64_t cmpccxadd_support:1;\n+ uint64_t tsc_aux_virtualization_support:1;\n+ uint64_t rmp_query_support:1;\n+ uint64_t bhi_no_support:1;\n+ uint64_t bhi_dis_support:1;\n+ uint64_t prefetch_i_support:1;\n+ uint64_t sha512_support:1;\n+ uint64_t mitigation_ctrl_support:1;\n+ uint64_t rfds_no_support:1;\n+ uint64_t rfds_clear_support:1;\n+ uint64_t sm3_support:1;\n+ uint64_t sm4_support:1;\n+ uint64_t secure_avic_support:1;\n+ uint64_t guest_intercept_ctrl_support:1;\n+ uint64_t sbpb_supported:1;\n+ uint64_t ibpb_br_type_supported:1;\n+ uint64_t srso_no_supported:1;\n+ uint64_t srso_user_kernel_no_supported:1;\n+ uint64_t vrew_clear_supported:1;\n+ uint64_t tsa_l1_no_supported:1;\n+ uint64_t tsa_sq_no_supported:1;\n+ uint64_t lass_support:1;\n+ uint64_t idle_hlt_intercept_support:1;\n+ uint64_t msr_list_support:1;\n+ };\n+};\n+\n enum hv_translate_gva_result_code {\n HV_TRANSLATE_GVA_SUCCESS = 0,\n \n","prefixes":["v4","1/9"]}