{"id":2223160,"url":"http://patchwork.ozlabs.org/api/patches/2223160/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414155433.483186-5-magnuskulke@linux.microsoft.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260414155433.483186-5-magnuskulke@linux.microsoft.com>","list_archive_url":null,"date":"2026-04-14T15:54:28","name":"[v4,4/9] target/i386/mshv: change cpuid mask to UINT32_MAX","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c4ee613b86ade11787da5e8fbf651016822136ac","submitter":{"id":90753,"url":"http://patchwork.ozlabs.org/api/people/90753/?format=json","name":"Magnus Kulke","email":"magnuskulke@linux.microsoft.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414155433.483186-5-magnuskulke@linux.microsoft.com/mbox/","series":[{"id":499862,"url":"http://patchwork.ozlabs.org/api/series/499862/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499862","date":"2026-04-14T15:54:24","name":"Support QEMU cpu models in MSHV accelerator","version":4,"mbox":"http://patchwork.ozlabs.org/series/499862/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223160/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223160/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=bpQWmU9+;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1776182088;\n bh=3qKH/AOjRjhm/x8a9eu7OnZ3TkDZ/w2V+YOycx7vrL0=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=bpQWmU9+TDGAd8CI/ETwYS6QrnfGycOi8tOYI5cadIT8535DNZszllAqmhHJJqS4P\n B6rax8RNxU2ayg1AzxU7/e8PfHF1fEw7YvVNmNrnRPF31By03SIR51tfxrvupz50zr\n 7Up70WEzVJ7Ky4w+YTIMPHxi3R5VpP5XLXcmsucI=","From":"Magnus Kulke ","To":"qemu-devel@nongnu.org","Cc":"Wei Liu , Wei Liu ,\n Magnus Kulke ,\n Magnus Kulke , Zhao Liu ,\n Paolo Bonzini ","Subject":"[PATCH v4 4/9] target/i386/mshv: change cpuid mask to UINT32_MAX","Date":"Tue, 14 Apr 2026 17:54:28 +0200","Message-Id":"<20260414155433.483186-5-magnuskulke@linux.microsoft.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260414155433.483186-1-magnuskulke@linux.microsoft.com>","References":"<20260414155433.483186-1-magnuskulke@linux.microsoft.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=13.77.154.182;\n envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com","X-Spam_score_int":"-42","X-Spam_score":"-4.3","X-Spam_bar":"----","X-Spam_report":"(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"The current implementation would only override the feature bits that are\nenabled, however we also want to consider disabled features, hence all\nbits are set on the masks in the hypercall argument.\n\nSigned-off-by: Magnus Kulke \nAcked-by: Wei Liu \n---\n target/i386/mshv/mshv-cpu.c | 17 ++++++-----------\n 1 file changed, 6 insertions(+), 11 deletions(-)","diff":"diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c\nindex 4183727a86..e42b5a614d 100644\n--- a/target/i386/mshv/mshv-cpu.c\n+++ b/target/i386/mshv/mshv-cpu.c\n@@ -538,22 +538,17 @@ static int register_intercept_result_cpuid_entry(const CPUState *cpu,\n .input.always_override = always_override,\n .input.padding = 0,\n /*\n- * With regard to masks - these are to specify bits to be overwritten\n- * The current CpuidEntry structure wouldn't allow to carry the masks\n- * in addition to the actual register values. For this reason, the\n- * masks are set to the exact values of the corresponding register bits\n- * to be registered for an overwrite. To view resulting values the\n- * hypervisor would return, HvCallGetVpCpuidValues hypercall can be\n- * used.\n+ * Masks specify which bits to override. Set to 0xFFFFFFFF to\n+ * override all bits with the values from the QEMU CPU model.\n */\n .result.eax = entry->eax,\n- .result.eax_mask = entry->eax,\n+ .result.eax_mask = 0xFFFFFFFF,\n .result.ebx = entry->ebx,\n- .result.ebx_mask = entry->ebx,\n+ .result.ebx_mask = 0xFFFFFFFF,\n .result.ecx = entry->ecx,\n- .result.ecx_mask = entry->ecx,\n+ .result.ecx_mask = 0xFFFFFFFF,\n .result.edx = entry->edx,\n- .result.edx_mask = entry->edx,\n+ .result.edx_mask = 0xFFFFFFFF,\n };\n union hv_register_intercept_result_parameters parameters = {\n .cpuid = cpuid_params,\n","prefixes":["v4","4/9"]}