{"id":2223107,"url":"http://patchwork.ozlabs.org/api/patches/2223107/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414132100.53861-2-philmd@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260414132100.53861-2-philmd@linaro.org>","list_archive_url":null,"date":"2026-04-14T13:20:57","name":"[PULL,1/3] hw/ppc/e500: fix bus-frequency property hardcoded to zero in CPU FDT node","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"827c01a9f6a654a29a8bbe586514293c075d3c09","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/?format=json","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414132100.53861-2-philmd@linaro.org/mbox/","series":[{"id":499841,"url":"http://patchwork.ozlabs.org/api/series/499841/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499841","date":"2026-04-14T13:20:57","name":"[PULL,1/3] hw/ppc/e500: fix bus-frequency property hardcoded to zero in CPU FDT node","version":1,"mbox":"http://patchwork.ozlabs.org/series/499841/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223107/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223107/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=bQ17769N;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::329;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Vivien LEGER \n\nThe bus-frequency property in the CPU FDT node was hardcoded to 0.\nThis is incorrect - it should reflect the actual platform bus clock\nfrequency, as firmware and RTOSes use it to derive peripheral clock\nrates.\n\nNotably, the RTEMS QorIQ BSP uses bus-frequency to program the MPIC\nglobal timer interval. With bus-frequency=0, the timer interval\noverflows to ~85 seconds, preventing any clock interrupts from firing.\n\nFix by adding a bus_freq field to PPCE500MachineClass and using it in\nthe FDT generator. Set bus_freq = PLATFORM_CLK_FREQ_HZ (400MHz) for\nexisting machines, matching the existing clock_freq value.\n\nSigned-off-by: Vivien LEGER \nReviewed-by: Bernhard Beschow \nMessage-ID: <20260411154535.1451361-1-vivien.leger@gmail.com>\nSigned-off-by: Philippe Mathieu-Daudé \n---\n hw/ppc/e500.h | 1 +\n hw/ppc/e500.c | 2 +-\n hw/ppc/e500plat.c | 1 +\n hw/ppc/mpc8544ds.c | 1 +\n 4 files changed, 4 insertions(+), 1 deletion(-)","diff":"diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h\nindex 11f8ae53177..6d56c7b4cb2 100644\n--- a/hw/ppc/e500.h\n+++ b/hw/ppc/e500.h\n@@ -40,6 +40,7 @@ struct PPCE500MachineClass {\n hwaddr pci_mmio_bus_base;\n hwaddr spin_base;\n uint32_t clock_freq;\n+ uint32_t bus_freq;\n uint32_t tb_freq;\n };\n \ndiff --git a/hw/ppc/e500.c b/hw/ppc/e500.c\nindex d6ca2e8563a..5be2f2095f6 100644\n--- a/hw/ppc/e500.c\n+++ b/hw/ppc/e500.c\n@@ -518,7 +518,7 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,\n env->icache_line_size);\n qemu_fdt_setprop_cell(fdt, cpu_name, \"d-cache-size\", 0x8000);\n qemu_fdt_setprop_cell(fdt, cpu_name, \"i-cache-size\", 0x8000);\n- qemu_fdt_setprop_cell(fdt, cpu_name, \"bus-frequency\", 0);\n+ qemu_fdt_setprop_cell(fdt, cpu_name, \"bus-frequency\", pmc->bus_freq);\n if (cpu->cpu_index) {\n qemu_fdt_setprop_string(fdt, cpu_name, \"status\", \"disabled\");\n qemu_fdt_setprop_string(fdt, cpu_name, \"enable-method\",\ndiff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c\nindex ca5647284d0..85cec810d9a 100644\n--- a/hw/ppc/e500plat.c\n+++ b/hw/ppc/e500plat.c\n@@ -94,6 +94,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, const void *data)\n pmc->pci_mmio_bus_base = 0xE0000000ULL;\n pmc->spin_base = 0xFEF000000ULL;\n pmc->clock_freq = PLATFORM_CLK_FREQ_HZ;\n+ pmc->bus_freq = PLATFORM_CLK_FREQ_HZ;\n pmc->tb_freq = PLATFORM_CLK_FREQ_HZ;\n \n mc->desc = \"generic paravirt e500 platform\";\ndiff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c\nindex 582698559d2..d022761cb6d 100644\n--- a/hw/ppc/mpc8544ds.c\n+++ b/hw/ppc/mpc8544ds.c\n@@ -56,6 +56,7 @@ static void mpc8544ds_machine_class_init(ObjectClass *oc, const void *data)\n pmc->pci_pio_base = 0xE1000000ULL;\n pmc->spin_base = 0xEF000000ULL;\n pmc->clock_freq = PLATFORM_CLK_FREQ_HZ;\n+ pmc->bus_freq = PLATFORM_CLK_FREQ_HZ;\n pmc->tb_freq = PLATFORM_CLK_FREQ_HZ;\n \n mc->desc = \"mpc8544ds\";\n","prefixes":["PULL","1/3"]}