{"id":2223047,"url":"http://patchwork.ozlabs.org/api/patches/2223047/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260414091422.16952-1-othacehe@gnu.org/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260414091422.16952-1-othacehe@gnu.org>","list_archive_url":null,"date":"2026-04-14T09:14:21","name":"misc: Add RZG2L OTP support","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"c92592e3499769fb56534756cd6affc4cb1aa935","submitter":{"id":87750,"url":"http://patchwork.ozlabs.org/api/people/87750/?format=json","name":"Mathieu Othacehe","email":"othacehe@gnu.org"},"delegate":{"id":1699,"url":"http://patchwork.ozlabs.org/api/users/1699/?format=json","username":"marex","first_name":"Marek","last_name":"Vasut","email":"marek.vasut@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260414091422.16952-1-othacehe@gnu.org/mbox/","series":[{"id":499804,"url":"http://patchwork.ozlabs.org/api/series/499804/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=499804","date":"2026-04-14T09:14:21","name":"misc: Add RZG2L OTP support","version":1,"mbox":"http://patchwork.ozlabs.org/series/499804/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223047/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223047/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gnu.org header.i=@gnu.org header.a=rsa-sha256\n header.s=fencepost-gnu-org header.b=HV3zCNKH;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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Tue, 14 Apr 2026 11:15:16 +0200 (CEST)","from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id AF72384181\n for ; Tue, 14 Apr 2026 11:15:13 +0200 (CEST)","from fencepost.gnu.org ([2001:470:142:3::e])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wCZrS-0007lT-Uk; Tue, 14 Apr 2026 05:15:10 -0400"],"X-Spam-Checker-Version":"SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,\n RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_PASS autolearn=ham\n autolearn_force=no version=3.4.2","DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=gnu.org;\n s=fencepost-gnu-org; h=MIME-Version:Date:Subject:To:From:in-reply-to:\n references; bh=vmuhiWU3GJC5V+H2xGHcBblO2Ri2WfsNdbqKl9f5hAQ=; b=HV3zCNKHNCSn4i\n 7aHixPeV+qxT/f2h2orJUTLXPhbEXh7bEcTvX50oNsaVBJ+tNaa65UsnyPr4qwyxeY7Hh9qV6rAZk\n znqPdRfNgpXsLgiqat4GHoPfY9kbbymfmMNun+MiwFS1jmUVnxPnR971MzYMDQ9dXn2w4PBrx/scI\n 8i4jAG211kujmmNzpOK8S+hQevNSzSOeyzrSTXeUM35qKgdE0UzotLR39SaGG2h63mP/lPzMCc5h7\n qMjbqxJWpQSS3iyYCqz1kUrio7VV1DNTYWOi7i8OUZ73tmiIN6Sj/FXHomkJJxigkwNLKRDGdUqsk\n bdacyGsmsqIwaHSg5QPw==;","From":"Mathieu Othacehe ","To":"Tom Rini ,\n Marek Vasut ,\n Paul Barker , Nobuhiro Iwamatsu ","Cc":"Mathieu Othacehe ,\n\tu-boot@lists.denx.de","Subject":"[PATCH] misc: Add RZG2L OTP support","Date":"Tue, 14 Apr 2026 11:14:21 +0200","Message-ID":"<20260414091422.16952-1-othacehe@gnu.org>","X-Mailer":"git-send-email 2.52.0","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"Add OTP support through the fuse command. Fusing is directly performed by\nU-Boot, which means that the trusted-firmware must allow the non-secure\nworld to perform fusing operations.\n\nSigned-off-by: Mathieu Othacehe \n---\n drivers/misc/Kconfig | 7 ++\n drivers/misc/Makefile | 1 +\n drivers/misc/rzg2l_otp.c | 222 +++++++++++++++++++++++++++++++++++++++\n 3 files changed, 230 insertions(+)\n create mode 100644 drivers/misc/rzg2l_otp.c","diff":"diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig\nindex ea785793d18..16cb800a393 100644\n--- a/drivers/misc/Kconfig\n+++ b/drivers/misc/Kconfig\n@@ -132,6 +132,13 @@ config SPL_ROCKCHIP_IODOMAIN\n \t for the IO-domain setting of the SoC to match the voltage supplied\n \t by the regulators.\n \n+config RZG2L_OTP\n+\tbool \"Renesas RZ/G2L OTP support\"\n+\tdepends on MISC\n+\thelp\n+\t Enable support for the OTP controller on\n+\t Renesas RZ/G2L SoCs.\n+\n config SIFIVE_OTP\n \tbool \"SiFive eMemory OTP driver\"\n \tdepends on MISC\ndiff --git a/drivers/misc/Makefile b/drivers/misc/Makefile\nindex e2170212e5a..64b2701b672 100644\n--- a/drivers/misc/Makefile\n+++ b/drivers/misc/Makefile\n@@ -69,6 +69,7 @@ obj-$(CONFIG_QCOM_GENI) += qcom_geni.o\n obj-$(CONFIG_$(PHASE_)ROCKCHIP_EFUSE) += rockchip-efuse.o\n obj-$(CONFIG_$(PHASE_)ROCKCHIP_OTP) += rockchip-otp.o\n obj-$(CONFIG_$(PHASE_)ROCKCHIP_IODOMAIN) += rockchip-io-domain.o\n+obj-$(CONFIG_RZG2L_OTP) += rzg2l_otp.o\n obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o\n obj-$(CONFIG_SIFIVE_OTP) += sifive-otp.o\n obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o\ndiff --git a/drivers/misc/rzg2l_otp.c b/drivers/misc/rzg2l_otp.c\nnew file mode 100644\nindex 00000000000..3aa3880e679\n--- /dev/null\n+++ b/drivers/misc/rzg2l_otp.c\n@@ -0,0 +1,222 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (C) 2026 Mathieu Othacehe \n+ */\n+#include \n+#include \n+#include \n+\n+/*\n+ * XXX: To enable direct fusing through U-Boot, the trusted-firmware must\n+ * allow the non-secure world to perform fusing operations. This is controlled\n+ * by the SYS_SLVACCCTL7 register.\n+ */\n+#define RZG2L_OTP_BASE 0x11860000\n+#define RZG2L_SYSC_BASE 0x11020000\n+\n+#define RZ_SYS_BASE_DEVID (RZG2L_SYSC_BASE + 0x0A04)\n+#define RZ_OTP_BASE_DEVID (RZG2L_OTP_BASE + 0x1178)\n+#define RZ_OTP_BASE_CHIPID (RZG2L_OTP_BASE + 0x1140)\n+\n+#define RZ_OTP_PWR (RZG2L_OTP_BASE + 0x0000)\n+#define RZ_OTP_STR (RZG2L_OTP_BASE + 0x0004)\n+#define RZ_OTP_STAWR (RZG2L_OTP_BASE + 0x0008)\n+#define RZ_OTP_ADRWR (RZG2L_OTP_BASE + 0x000c)\n+#define RZ_OTP_DATAWR (RZG2L_OTP_BASE + 0x0010)\n+\n+#define RZ_OTP_ADRRD (RZG2L_OTP_BASE + 0x0014)\n+#define RZ_OTP_DATARD (RZG2L_OTP_BASE + 0x0018)\n+\n+#define RZ_OTP_FLAG (RZG2L_OTP_BASE + 0x001c)\n+\n+#define OTP_PWR\t\t BIT(0)\n+#define ERR_WR_1\t BIT(1)\n+#define ERR_WR_2\t BIT(2)\n+#define ERR_WP\t\t BIT(3)\n+#define OTP_ACCL\t BIT(4)\n+#define ERR_RDY_WR\t BIT(8)\n+#define OTP_DUMMY_READ\t (0x400 >> 2)\n+\n+static int rzg2l_otp_open(void)\n+{\n+\tint i = 0;\n+\n+\tif (readl(RZ_OTP_PWR) & 1) {\n+\t\tdebug(\"OTP already powered up\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\twhile ((readl(RZ_OTP_STR) & 1) ||\n+\t ((readl(RZ_OTP_FLAG) & 1) == 0)) {\n+\t\tif (i++ > 1000) {\n+\t\t\tprintf(\"OTP power-up timeout\\n\");\n+\t\t\treturn -ETIMEDOUT;\n+\t\t}\n+\n+\t\tmdelay(1);\n+\t}\n+\n+\twritel(readl(RZ_OTP_PWR) | OTP_PWR | OTP_ACCL, RZ_OTP_PWR);\n+\n+\treturn 0;\n+}\n+\n+static int rzg2l_otp_dummy_read(void)\n+{\n+\tint i = 0;\n+\n+\twhile ((readl(RZ_OTP_STR) & 1) == 0) {\n+\t\tif (i++ > 1000) {\n+\t\t\tprintf(\"Timeout polling ready for OTP read\\n\");\n+\t\t\treturn -ETIMEDOUT;\n+\t\t}\n+\t\tmdelay(1);\n+\t}\n+\n+\twritel(RZG2L_OTP_BASE + OTP_DUMMY_READ, RZ_OTP_ADRRD);\n+\treadl(RZ_OTP_DATARD);\n+\n+\treturn 0;\n+}\n+\n+static int rzg2l_otp_close(void)\n+{\n+\tint i = 0;\n+\tu32 val;\n+\n+\trzg2l_otp_dummy_read();\n+\n+\tval = readl(RZ_OTP_PWR);\n+\tval = val & OTP_PWR & OTP_ACCL;\n+\twritel(val, RZ_OTP_PWR);\n+\n+\twhile (readl(RZ_OTP_STR) & 1) {\n+\t\tif (i++ > 1000) {\n+\t\t\tprintf(\"Timeout leaving OTP ready state\\n\");\n+\t\t\treturn -ETIMEDOUT;\n+\t\t}\n+\t\tmdelay(1);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int rzg2l_otp_read_word(u32 addr, u32 *val)\n+{\n+\tint i = 0;\n+\tint ret;\n+\n+\tret = rzg2l_otp_open();\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\twhile ((readl(RZ_OTP_STR) & 1) == 0) {\n+\t\tif (i++ > 1000) {\n+\t\t\tprintf(\"Timeout polling ready for OTP read\\n\");\n+\t\t\trzg2l_otp_close();\n+\t\t\treturn -ETIMEDOUT;\n+\t\t}\n+\t\tmdelay(1);\n+\t}\n+\n+\twritel(addr, RZ_OTP_ADRRD);\n+\t*val = readl(RZ_OTP_DATARD);\n+\n+\tret = rzg2l_otp_close();\n+\n+\treturn ret;\n+}\n+\n+static int rzg2l_otp_program_word(u32 addr, u32 val)\n+{\n+\tint i = 0;\n+\tint ret;\n+\tu32 otpval;\n+\n+\tret = rzg2l_otp_open();\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\twhile ((readl(RZ_OTP_STR) & 1) == 0) {\n+\t\tif (i++ > 1000) {\n+\t\t\tprintf(\"Timeout polling ready for OTP write\\n\");\n+\t\t\tgoto close;\n+\t\t}\n+\t\tmdelay(1);\n+\t}\n+\n+\twritel(addr, RZ_OTP_ADRWR);\n+\twritel(val, RZ_OTP_DATAWR);\n+\n+\twritel(1, RZ_OTP_STAWR);\n+\n+\tif (readl(RZ_OTP_STR) & ERR_RDY_WR) {\n+\t\tprintf(\"OTP not ready for write\\n\");\n+\t\twritel(readl(RZ_OTP_STR) & ERR_RDY_WR, RZ_OTP_STR);\n+\t\tgoto close;\n+\t}\n+\n+\ti = 0;\n+\twhile ((readl(RZ_OTP_STR) & 1) == 0 ||\n+\t (readl(RZ_OTP_STAWR) & 1)) {\n+\t\tif (i++ > 1000) {\n+\t\t\tprintf(\"Timeout polling OTP write finished\\n\");\n+\t\t\tgoto close;\n+\t\t}\n+\n+\t\tmdelay(1);\n+\t}\n+\n+\tif ((readl(RZ_OTP_STR) & ERR_WP) ||\n+\t (readl(RZ_OTP_STR) & ERR_WR_1) ||\n+\t (readl(RZ_OTP_STR) & ERR_WR_2)) {\n+\t\tprintf(\"OTP write error (protected or invalid)\\n\");\n+\t\tgoto close;\n+\t}\n+\n+\twritel(addr, RZ_OTP_ADRRD);\n+\totpval = readl(RZ_OTP_DATARD);\n+\n+\tif (otpval != val) {\n+\t\tprintf(\"OTP verify failed: wrote 0x%08x read 0x%08x\\n\",\n+\t\t val, otpval);\n+\t\tgoto close;\n+\t}\n+\n+close:\n+\tret = rzg2l_otp_close();\n+\treturn ret;\n+}\n+\n+/* ---------------------------------------------------------------- */\n+/* U-Boot fuse API */\n+\n+int fuse_read(u32 bank, u32 word, u32 *val)\n+{\n+\tu32 addr;\n+\n+\taddr = RZG2L_OTP_BASE + (word >> 2);\n+\n+\treturn rzg2l_otp_read_word(addr, val);\n+}\n+\n+int fuse_prog(u32 bank, u32 word, u32 val)\n+{\n+\tu32 addr;\n+\n+\taddr = RZG2L_OTP_BASE + (word >> 2);\n+\n+\treturn rzg2l_otp_program_word(addr, val);\n+}\n+\n+int fuse_sense(u32 bank, u32 word, u32 *val)\n+{\n+\t/* not supported */\n+\treturn -ENOSYS;\n+}\n+\n+int fuse_override(u32 bank, u32 word, u32 val)\n+{\n+\t/* not supported */\n+\treturn -ENOSYS;\n+}\n","prefixes":[]}