{"id":2223020,"url":"http://patchwork.ozlabs.org/api/patches/2223020/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20260414082141.763453-1-wangzicong@masscore.cn/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260414082141.763453-1-wangzicong@masscore.cn>","list_archive_url":null,"date":"2026-04-14T08:21:41","name":"RISC-V: Make tuple vector not tieable to some modes.","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f874fac217309b1554ea88c42cc650c5171e7834","submitter":{"id":93140,"url":"http://patchwork.ozlabs.org/api/people/93140/?format=json","name":"wangzicong","email":"wangzicong@masscore.cn"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20260414082141.763453-1-wangzicong@masscore.cn/mbox/","series":[{"id":499801,"url":"http://patchwork.ozlabs.org/api/series/499801/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=499801","date":"2026-04-14T08:21:41","name":"RISC-V: Make tuple vector not tieable to some modes.","version":1,"mbox":"http://patchwork.ozlabs.org/series/499801/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223020/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223020/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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Without this patch some unnecessary type conversions \nmay occur, especially when zvl is specified. \nE.g. RVVMF2x4HI and RVVM2DI are tieable in gcc trunk, and when extracting \nan inner vector mode RVVMF2HI from RVVMF2x4HI and zvl is specified, it will \nbe converted to DI, which is not expected.\n\n PR 124448\n\ngcc/ChangeLog:\n\n * config/riscv/riscv.cc (riscv_modes_tieable_p):\n Make tuple vector modes not tieable to vector modes with different \n inner mode.\n\ngcc/testsuite/ChangeLog:\n\n * gcc.target/riscv/rvv/autovec/pr124448.c: New test.\n\nSigned-off-by: Zicong Wang \n\n---\n gcc/config/riscv/riscv.cc | 25 +++++++++++++\n .../gcc.target/riscv/rvv/autovec/pr124448.c | 37 +++++++++++++++++++\n 2 files changed, 62 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c","diff":"diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc\nindex a6106547757..9aba7b763fc 100644\n--- a/gcc/config/riscv/riscv.cc\n+++ b/gcc/config/riscv/riscv.cc\n@@ -10897,6 +10897,31 @@ riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2)\n E.g. V2SI and DI are not tieable. */\n if (riscv_vector_mode_p (mode1) != riscv_vector_mode_p (mode2))\n return false;\n+\n+ /* We don't allow tuple vector modes to be tied to any vector mode\n+ that has different inner mode. It may cause unnecessary type\n+ conversions.\n+ E.g. RVVMF2x4HI and RVVM2DI are not tieable. */\n+ if (riscv_tuple_mode_p (mode1) || riscv_tuple_mode_p (mode2))\n+ {\n+ machine_mode subpart_mode1, subpart_mode2;\n+ if (riscv_tuple_mode_p (mode1))\n+ {\n+ subpart_mode1 = riscv_vector::get_subpart_mode (mode1);\n+ subpart_mode1 = GET_MODE_INNER (subpart_mode1);\n+ }\n+ else\n+ subpart_mode1 = GET_MODE_INNER (mode1);\n+ if (riscv_tuple_mode_p (mode2))\n+ {\n+ subpart_mode2 = riscv_vector::get_subpart_mode (mode2);\n+ subpart_mode2 = GET_MODE_INNER (subpart_mode2);\n+ }\n+ else\n+ subpart_mode2 = GET_MODE_INNER (mode2);\n+ if (subpart_mode1 != subpart_mode2)\n+ return false;\n+ }\n return (mode1 == mode2\n \t || !(GET_MODE_CLASS (mode1) == MODE_FLOAT\n \t && GET_MODE_CLASS (mode2) == MODE_FLOAT));\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c\nnew file mode 100644\nindex 00000000000..fd74c509849\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c\n@@ -0,0 +1,37 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-march=rv64gcv_zvl128b -O3 -mrvv-vector-bits=zvl\" } */\n+/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-O1\" \"-O2\" \"-Os\" \"-Og\" \"-Oz\" } } */\n+\n+#include \n+\n+void dct( int16_t d[16], int16_t dct[16] )\n+{\n+ int16_t tmp[16];\n+ for( int i = 0; i < 4; i++ )\n+ {\n+ int s03 = d[i*4+0] + d[i*4+3];\n+ int s12 = d[i*4+1] + d[i*4+2];\n+ int d03 = d[i*4+0] - d[i*4+3];\n+ int d12 = d[i*4+1] - d[i*4+2];\n+ tmp[0*4+i] = s03 + s12;\n+ tmp[1*4+i] = 2*d03 + d12;\n+ tmp[2*4+i] = s03 - s12;\n+ tmp[3*4+i] = d03 - 2*d12;\n+ }\n+ for( int i = 0; i < 4; i++ )\n+ {\n+ int s03 = tmp[i*4+0] + tmp[i*4+3];\n+ int s12 = tmp[i*4+1] + tmp[i*4+2];\n+ int d03 = tmp[i*4+0] - tmp[i*4+3];\n+ int d12 = tmp[i*4+1] - tmp[i*4+2];\n+\n+ dct[i*4+0] = s03 + s12;\n+ dct[i*4+1] = 2*d03 + d12;\n+ dct[i*4+2] = s03 - s12;\n+ dct[i*4+3] = d03 - 2*d12;\n+ }\n+}\n+\n+/* { dg-final { scan-assembler-times {vsetivli} 1 } } */\n+/* { dg-final { scan-assembler-not {vslidedown\\.vi} } } */\n+\n","prefixes":[]}