{"id":2223005,"url":"http://patchwork.ozlabs.org/api/patches/2223005/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414080025.3005916-4-jamin_lin@aspeedtech.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260414080025.3005916-4-jamin_lin@aspeedtech.com>","list_archive_url":null,"date":"2026-04-14T08:00:29","name":"[v2,03/17] hw/usb/hcd-ehci.c: Fix coding style issues reported by checkpatch","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"731c7be84df6991195f1ee06e17e672fa5160eb0","submitter":{"id":81768,"url":"http://patchwork.ozlabs.org/api/people/81768/?format=json","name":"Jamin Lin","email":"jamin_lin@aspeedtech.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414080025.3005916-4-jamin_lin@aspeedtech.com/mbox/","series":[{"id":499795,"url":"http://patchwork.ozlabs.org/api/series/499795/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499795","date":"2026-04-14T08:00:26","name":"hw/usb/ehci: Add 64-bit descriptor addressing support","version":2,"mbox":"http://patchwork.ozlabs.org/series/499795/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2223005/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2223005/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=McGoGWTY;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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\\\n- val &= ~ field##_MASK; \\\n+ val &= ~field##_MASK; \\\n val |= ((newval) << field##_SH) & field##_MASK; \\\n *data = val; \\\n- } while(0)\n+ } while (0)\n \n static const char *ehci_state_names[] = {\n [EST_INACTIVE] = \"INACTIVE\",\n@@ -472,8 +474,10 @@ static bool ehci_verify_pid(EHCIQueue *q, EHCIqtd *qtd)\n }\n }\n \n-/* Finish executing and writeback a packet outside of the regular\n- fetchqh -> fetchqtd -> execute -> writeback cycle */\n+/*\n+ * Finish executing and writeback a packet outside of the regular\n+ * fetchqh -> fetchqtd -> execute -> writeback cycle\n+ */\n static void ehci_writeback_async_complete_packet(EHCIPacket *p)\n {\n EHCIQueue *q = p->queue;\n@@ -733,7 +737,7 @@ static void ehci_detach(USBPort *port)\n ehci_queues_rip_device(s, port->dev, 0);\n ehci_queues_rip_device(s, port->dev, 1);\n \n- *portsc &= ~(PORTSC_CONNECT|PORTSC_PED|PORTSC_SUSPEND);\n+ *portsc &= ~(PORTSC_CONNECT | PORTSC_PED | PORTSC_SUSPEND);\n *portsc |= PORTSC_CSC;\n \n ehci_raise_irq(s, USBSTS_PCD);\n@@ -858,7 +862,7 @@ void ehci_reset(void *opaque)\n * Do the detach before touching portsc, so that it correctly gets send to\n * us or to our companion based on PORTSC_POWNER before the reset.\n */\n- for(i = 0; i < EHCI_PORTS; i++) {\n+ for (i = 0; i < EHCI_PORTS; i++) {\n devs[i] = s->ports[i].dev;\n if (devs[i] && devs[i]->attached) {\n usb_detach(&s->ports[i]);\n@@ -877,7 +881,7 @@ void ehci_reset(void *opaque)\n s->astate = EST_INACTIVE;\n s->pstate = EST_INACTIVE;\n \n- for(i = 0; i < EHCI_PORTS; i++) {\n+ for (i = 0; i < EHCI_PORTS; i++) {\n if (s->companion_ports[i]) {\n s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;\n } else {\n@@ -942,8 +946,9 @@ static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)\n uint32_t *portsc = &s->portsc[port];\n uint32_t orig;\n \n- if (s->companion_ports[port] == NULL)\n+ if (s->companion_ports[port] == NULL) {\n return;\n+ }\n \n owner = owner & PORTSC_POWNER;\n orig = *portsc & PORTSC_POWNER;\n@@ -988,7 +993,7 @@ static void ehci_port_write(void *ptr, hwaddr addr,\n trace_usb_ehci_port_reset(port, 1);\n }\n \n- if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {\n+ if (!(val & PORTSC_PRESET) && (*portsc & PORTSC_PRESET)) {\n trace_usb_ehci_port_reset(port, 0);\n if (dev && dev->attached) {\n usb_port_reset(&s->ports[port]);\n@@ -1065,8 +1070,10 @@ static void ehci_opreg_write(void *ptr, hwaddr addr,\n break;\n \n case USBSTS:\n- val &= USBSTS_RO_MASK; // bits 6 through 31 are RO\n- ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC\n+ /* bits 6 through 31 are RO */\n+ val &= USBSTS_RO_MASK;\n+ /* bits 0 through 5 are R/WC */\n+ ehci_clear_usbsts(s, val);\n val = s->usbsts;\n ehci_update_irq(s);\n break;\n@@ -1131,8 +1138,7 @@ static void ehci_flush_qh(EHCIQueue *q)\n put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);\n }\n \n-// 4.10.2\n-\n+/* 4.10.2 */\n static int ehci_qh_do_overlay(EHCIQueue *q)\n {\n EHCIPacket *p = QTAILQ_FIRST(&q->packets);\n@@ -1145,8 +1151,7 @@ static int ehci_qh_do_overlay(EHCIQueue *q)\n assert(p != NULL);\n assert(p->qtdaddr == q->qtdaddr);\n \n- // remember values in fields to preserve in qh after overlay\n-\n+ /* remember values in fields to preserve in qh after overlay */\n dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;\n ping = q->qh.token & QTD_TOKEN_PING;\n \n@@ -1170,7 +1175,7 @@ static int ehci_qh_do_overlay(EHCIQueue *q)\n }\n \n if (!(q->qh.epchar & QH_EPCHAR_DTC)) {\n- // preserve QH DT bit\n+ /* preserve QH DT bit */\n q->qh.token &= ~QTD_TOKEN_DTOGGLE;\n q->qh.token |= dtoggle;\n }\n@@ -1397,9 +1402,7 @@ static int ehci_execute(EHCIPacket *p, const char *action)\n return 1;\n }\n \n-/* 4.7.2\n- */\n-\n+/* 4.7.2 */\n static int ehci_process_itd(EHCIState *ehci,\n EHCIitd *itd,\n uint32_t addr)\n@@ -1411,13 +1414,13 @@ static int ehci_process_itd(EHCIState *ehci,\n \n ehci->periodic_sched_active = PERIODIC_ACTIVE;\n \n- dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);\n+ dir = (itd->bufptr[1] & ITD_BUFPTR_DIRECTION);\n devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);\n endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);\n max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);\n mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);\n \n- for(i = 0; i < 8; i++) {\n+ for (i = 0; i < 8; i++) {\n if (itd->transact[i] & ITD_XACT_ACTIVE) {\n pg = get_field(itd->transact[i], ITD_XACT_PGSEL);\n off = itd->transact[i] & ITD_XACT_OFFSET_MASK;\n@@ -1513,8 +1516,9 @@ static int ehci_process_itd(EHCIState *ehci,\n }\n \n \n-/* This state is the entry point for asynchronous schedule\n- * processing. Entry here constitutes a EHCI start event state (4.8.5)\n+/*\n+ * This state is the entry point for asynchronous schedule\n+ * processing. Entry here constitutes a EHCI start event state (4.8.5)\n */\n static int ehci_state_waitlisthead(EHCIState *ehci, int async)\n {\n@@ -1531,7 +1535,7 @@ static int ehci_state_waitlisthead(EHCIState *ehci, int async)\n ehci_queues_rip_unused(ehci, async);\n \n /* Find the head of the list (4.9.1.1) */\n- for(i = 0; i < MAX_QH; i++) {\n+ for (i = 0; i < MAX_QH; i++) {\n if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,\n sizeof(EHCIqh) >> 2) < 0) {\n return 0;\n@@ -1564,8 +1568,9 @@ out:\n }\n \n \n-/* This state is the entry point for periodic schedule processing as\n- * well as being a continuation state for async processing.\n+/*\n+ * This state is the entry point for periodic schedule processing as\n+ * well as being a continuation state for async processing.\n */\n static int ehci_state_fetchentry(EHCIState *ehci, int async)\n {\n@@ -1674,7 +1679,7 @@ static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)\n \n #if EHCI_DEBUG\n if (q->qhaddr != q->qh.next) {\n- DPRINTF(\"FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\\n\",\n+ DPRINTF(\"FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\\n\",\n q->qhaddr,\n q->qh.epchar & QH_EPCHAR_H,\n q->qh.token & QTD_TOKEN_HALT,\n@@ -1924,8 +1929,10 @@ static int ehci_state_execute(EHCIQueue *q)\n return -1;\n }\n \n- // TODO verify enough time remains in the uframe as in 4.4.1.1\n- // TODO write back ptr to async list when done or out of time\n+ /*\n+ * TODO verify enough time remains in the uframe as in 4.4.1.1\n+ * TODO write back ptr to async list when done or out of time\n+ */\n \n /* 4.10.3, bottom of page 82, go horizontal on transaction counter == 0 */\n if (!q->async && q->transact_ctr == 0) {\n@@ -2036,7 +2043,7 @@ static void ehci_advance_state(EHCIState *ehci, int async)\n int again;\n \n do {\n- switch(ehci_get_state(ehci, async)) {\n+ switch (ehci_get_state(ehci, async)) {\n case EST_WAITLISTHEAD:\n again = ehci_state_waitlisthead(ehci, async);\n break;\n@@ -2115,21 +2122,20 @@ static void ehci_advance_state(EHCIState *ehci, int async)\n ehci_reset(ehci);\n again = 0;\n }\n- }\n- while (again);\n+ } while (again);\n }\n \n static void ehci_advance_async_state(EHCIState *ehci)\n {\n const int async = 1;\n \n- switch(ehci_get_state(ehci, async)) {\n+ switch (ehci_get_state(ehci, async)) {\n case EST_INACTIVE:\n if (!ehci_async_enabled(ehci)) {\n break;\n }\n ehci_set_state(ehci, async, EST_ACTIVE);\n- // No break, fall through to ACTIVE\n+ /* No break, fall through to ACTIVE */\n \n case EST_ACTIVE:\n if (!ehci_async_enabled(ehci)) {\n@@ -2153,7 +2159,8 @@ static void ehci_advance_async_state(EHCIState *ehci)\n ehci_set_state(ehci, async, EST_WAITLISTHEAD);\n ehci_advance_state(ehci, async);\n \n- /* If the doorbell is set, the guest wants to make a change to the\n+ /*\n+ * If the doorbell is set, the guest wants to make a change to the\n * schedule. The host controller needs to release cached data.\n * (section 4.8.2)\n */\n@@ -2180,13 +2187,13 @@ static void ehci_advance_periodic_state(EHCIState *ehci)\n uint32_t list;\n const int async = 0;\n \n- // 4.6\n+ /* 4.6 */\n \n- switch(ehci_get_state(ehci, async)) {\n+ switch (ehci_get_state(ehci, async)) {\n case EST_INACTIVE:\n if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) {\n ehci_set_state(ehci, async, EST_ACTIVE);\n- // No break, fall through to ACTIVE\n+ /* No break, fall through to ACTIVE */\n } else\n break;\n \n@@ -2210,7 +2217,7 @@ static void ehci_advance_periodic_state(EHCIState *ehci)\n \n DPRINTF(\"PERIODIC state adv fr=%d. [%08X] -> %08X\\n\",\n ehci->frindex / 8, list, entry);\n- ehci_set_fetch_addr(ehci, async,entry);\n+ ehci_set_fetch_addr(ehci, async, entry);\n ehci_set_state(ehci, async, EST_FETCHENTRY);\n ehci_advance_state(ehci, async);\n ehci_queues_rip_unused(ehci, async);\n@@ -2235,7 +2242,8 @@ static void ehci_update_frindex(EHCIState *ehci, int uframes)\n ehci_raise_irq(ehci, USBSTS_FLR);\n }\n \n- /* How many times will frindex roll over 0x4000 with this frame count?\n+ /*\n+ * How many times will frindex roll over 0x4000 with this frame count?\n * usbsts_frindex is decremented by 0x4000 on rollover until it reaches 0\n */\n int rollovers = (ehci->frindex + uframes) / 0x4000;\n@@ -2315,8 +2323,9 @@ static void ehci_work_bh(void *opaque)\n ehci->async_stepdown++;\n }\n \n- /* Async is not inside loop since it executes everything it can once\n- * called\n+ /*\n+ * Async is not inside loop since it executes everything it can once\n+ * called\n */\n if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) {\n need_timer++;\n@@ -2334,15 +2343,18 @@ static void ehci_work_bh(void *opaque)\n }\n \n if (need_timer) {\n- /* If we've raised int, we speed up the timer, so that we quickly\n- * notice any new packets queued up in response */\n+ /*\n+ * If we've raised int, we speed up the timer, so that we quickly\n+ * notice any new packets queued up in response\n+ */\n if (ehci->int_req_by_async && (ehci->usbsts & USBSTS_INT)) {\n expire_time = t_now +\n NANOSECONDS_PER_SECOND / (FRAME_TIMER_FREQ * 4);\n ehci->int_req_by_async = false;\n } else {\n- expire_time = t_now + (NANOSECONDS_PER_SECOND\n- * (ehci->async_stepdown+1) / FRAME_TIMER_FREQ);\n+ expire_time = t_now\n+ + (NANOSECONDS_PER_SECOND * (ehci->async_stepdown + 1) /\n+ FRAME_TIMER_FREQ);\n }\n timer_mod(ehci->frame_timer, expire_time);\n }\n","prefixes":["v2","03/17"]}